Andrew Lenharth dd3ccde9ea it helps if your conditionals are not reversed ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24641 91177308-0d34-0410-b5e6-96231b3b80d8		2005-12-09 00:45:42 +00:00
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Alpha	it helps if your conditionals are not reversed	2005-12-09 00:45:42 +00:00
CBackend
IA64	Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted.	2005-12-05 02:34:29 +00:00
PowerPC	Add another important case we miss	2005-12-08 07:13:28 +00:00
Skeleton	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
Sparc	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
SparcV8	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
SparcV9	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
X86	Added explicit type field to ComplexPattern.	2005-12-08 02:15:07 +00:00
Makefile
MRegisterInfo.cpp
SubtargetFeature.cpp
Target.td	* Added instruction property hasCtrlDep for those which r/w control-flow	2005-12-04 08:13:17 +00:00
TargetData.cpp
TargetFrameInfo.cpp
TargetInstrInfo.cpp
TargetMachine.cpp
TargetMachineRegistry.cpp
TargetSchedInfo.cpp
TargetSchedule.td
TargetSelectionDAG.td	Added support for ComplexPattern.	2005-12-08 04:28:48 +00:00
TargetSubtarget.cpp