Sanjoy Das a0a0b40aa3 Bugfix: SCEVExpander incorrectly marks increment operations as no-wrap ... (The change was landed in r230280 and caused the regression PR22674. This version contains a fix and a test-case for PR22674). When emitting the increment operation, SCEVExpander marks the operation as nuw or nsw based on the flags on the preincrement SCEV. This is incorrect because, for instance, it is possible that {-6,+,1} is <nuw> while {-6,+,1}+1 = {-5,+,1} is not. This change teaches SCEV to mark the increment as nuw/nsw only if it can explicitly prove that the increment operation won't overflow. Apart from the attached test case, another (more realistic) manifestation of the bug can be seen in Transforms/IndVarSimplify/pr20680.ll. Differential Revision: http://reviews.llvm.org/D7778 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230533 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-25 20:02:59 +00:00
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AArch64	Bugfix: SCEVExpander incorrectly marks increment operations as no-wrap	2015-02-25 20:02:59 +00:00
ARM	Improve handling of stack accesses in Thumb-1	2015-02-25 14:41:06 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips	[MIPS]Multiple and add instructions for Mips are currently available in mips32r2/mips64r2 and later but should also be available in mips4, mips5, and mips64. This patch fixes the requested features and updates the corresponding test files.	2015-02-25 15:24:37 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add triples to QPX tests	2015-02-25 01:26:59 +00:00
R600	R600/SI: Remove isel mubuf legalization	2015-02-24 17:59:19 +00:00
SPARC
SystemZ
Thumb	Improve handling of stack accesses in Thumb-1	2015-02-25 14:41:06 +00:00
Thumb2
X86	Bugfix: SCEVExpander incorrectly marks increment operations as no-wrap	2015-02-25 20:02:59 +00:00
XCore