llvm-6502/test/CodeGen/AArch64/fast-isel-vret.ll
Juergen Ributzka c0f00e90d2 [FastISel][AArch64] Add missing test case for previous commit.
This adds the missing test case for the previous commit:
Allow handling of vectors during return lowering for little endian machines.

Sorry for the noise.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217847 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-15 23:47:57 +00:00

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LLVM

; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
; Test that we don't abort fast-isle for ret
define <8 x i8> @ret_v8i8(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: ret_v8i8
; CHECK: add.8b v0, v0, v1
%1 = add <8 x i8> %a, %b
ret <8 x i8> %1
}