Evan Cheng de8aa4ed9c Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103104 91177308-0d34-0410-b5e6-96231b3b80d8		2010-05-05 18:28:36 +00:00
..
Analysis	Use the SCEVAddRecExpr::getPostIncExpr utility function instead	2010-05-04 01:12:27 +00:00
Archive	silence a warning, patch by "mike".	2010-04-25 04:44:26 +00:00
AsmParser	Remove the API compatibility layer which converted add, sub, and mul	2010-05-03 22:44:19 +00:00
Bitcode	Revert 101465, it broke internal OpenGL testing.	2010-04-16 23:37:20 +00:00
CodeGen	Teach liveintervalanalysis about virtual registers which are defined by reg_sequence instructions that are formed by registers defined by distinct instructions. e.g.	2010-05-05 18:27:40 +00:00
CompilerDriver
ExecutionEngine	Remove the -enable-sjlj-eh option, which doesn't do anything.	2010-05-02 15:36:26 +00:00
Linker
MC	MC: Rename MCSymbol::{g,s}etValue -> MCSymbol::{g,s}etVariableValue.	2010-05-05 17:41:00 +00:00
Support	Try again if write(2) reports an recoverable error.	2010-05-05 15:17:47 +00:00
System	This doesn't need SmallVector.h anymore.	2010-04-19 17:51:31 +00:00
Target	Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.	2010-05-05 18:28:36 +00:00
Transforms	Combine the implementations of the core part of the SSAUpdater and	2010-05-04 23:18:19 +00:00
VMCore	Fix a problem exposed by my previous commit and noticed by a release-asserts	2010-05-04 14:25:42 +00:00
Makefile