Matt Arsenault e0e503801f R600: Add a testcase for sext_in_reg I missed. ... This sext_inreg i32 in i64 case was already handled, but not enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204840 91177308-0d34-0410-b5e6-96231b3b80d8		2014-03-26 18:31:06 +00:00
..
InstPrinter	Make methods static	2014-03-17 22:23:09 +00:00
MCTargetDesc
TargetInfo
AMDGPU.h
AMDGPU.td
AMDGPUAsmPrinter.cpp	R600/SI: Use correct dest register class for V_READFIRSTLANE_B32	2014-03-17 17:03:51 +00:00
AMDGPUAsmPrinter.h
AMDGPUCallingConv.td
AMDGPUConvertToISA.cpp
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td	R600: Match sign_extend_inreg to BFE instructions	2014-03-17 18:58:11 +00:00
AMDGPUInstructions.td	R600: Reorganize tablegen instruction definitions	2014-03-24 16:07:25 +00:00
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp
AMDGPUISelLowering.cpp	R600: Add a testcase for sext_in_reg I missed.	2014-03-26 18:31:06 +00:00
AMDGPUISelLowering.h	R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp	2014-03-25 18:18:27 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp
AMDGPUMCInstLower.h
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp
AMDGPUSubtarget.h	R600: Match sign_extend_inreg to BFE instructions	2014-03-17 18:58:11 +00:00
AMDGPUTargetMachine.cpp	R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()	2014-03-21 15:51:57 +00:00
AMDGPUTargetMachine.h
AMDGPUTargetTransformInfo.cpp
AMDILBase.td
AMDILCFGStructurizer.cpp	R600: Don't viewCFG() under DEBUG() except on failure.	2014-03-24 20:29:02 +00:00
AMDILInstrInfo.td
AMDILIntrinsicInfo.cpp
AMDILIntrinsicInfo.h
AMDILIntrinsics.td	R600: Match sign_extend_inreg to BFE instructions	2014-03-17 18:58:11 +00:00
AMDILISelLowering.cpp	R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp	2014-03-25 18:18:27 +00:00
AMDILRegisterInfo.td
CaymanInstructions.td	R600: Reorganize tablegen instruction definitions	2014-03-24 16:07:25 +00:00
CMakeLists.txt
EvergreenInstructions.td	R600: Reorganize tablegen instruction definitions	2014-03-24 16:07:25 +00:00
LLVMBuild.txt
Makefile
Processors.td
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td	R600: Reorganize tablegen instruction definitions	2014-03-24 16:07:25 +00:00
R600Intrinsics.td
R600ISelLowering.cpp	R600: Match sign_extend_inreg to BFE instructions	2014-03-17 18:58:11 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td	R600: Reorganize tablegen instruction definitions	2014-03-24 16:07:25 +00:00
SIAnnotateControlFlow.cpp
SIDefines.h
SIFixSGPRCopies.cpp
SIInsertWaits.cpp
SIInstrFormats.td	R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()	2014-03-21 15:51:57 +00:00
SIInstrInfo.cpp	R600/SI: Fix extra mov from legalizing 64-bit SALU ops.	2014-03-24 20:08:13 +00:00
SIInstrInfo.h	R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.	2014-03-24 20:08:09 +00:00
SIInstrInfo.td	R600/SI: Add unused LDS 2 form instructions.	2014-03-19 22:19:56 +00:00
SIInstructions.td	R600/SI: Fix 64-bit bit ops that require the VALU.	2014-03-24 20:08:05 +00:00
SIIntrinsics.td
SIISelLowering.cpp	R600/SI: Fix 64-bit private loads.	2014-03-24 17:50:46 +00:00
SIISelLowering.h
SILowerControlFlow.cpp	R600/SI: Use correct dest register class for V_READFIRSTLANE_B32	2014-03-17 17:03:51 +00:00
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIRegisterInfo.cpp
SIRegisterInfo.h
SIRegisterInfo.td	R600/SI: Use correct dest register class for V_READFIRSTLANE_B32	2014-03-17 17:03:51 +00:00
SISchedule.td
SITypeRewriter.cpp