Daniel Sanders 7858e495e9 [mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V ... Summary: These processors will only be available for the integrated assembler at first (CodeGen will emit a fatal error saying they are not implemented). The intention is to work through the existing instructions and correctly annotate the ISA they were added in so that we have a sufficiently good base to start MIPS64r6 development. MIPS64r6 removes/re-encodes certain instructions and I believe it is best to define ISA's using set-union's as far as possible rather than using set-subtraction. Reviewers: vmedic Subscribers: emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D3569 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208221 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-07 16:25:22 +00:00
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AArch64	AArch64/ARM64: add two more MC tests to ARM64 set.	2014-05-06 12:50:58 +00:00
ARM	ARM: For thumb fixups store halfwords high first and low second	2014-05-06 10:05:11 +00:00
ARM64	AArch64/ARM64: make NEON vector list parsing a bit more robust	2014-05-06 12:50:51 +00:00
AsmParser	Integrated assbemler, macros: added 'vararg' argument qualifier support.	2014-04-23 06:56:28 +00:00
COFF	MC: place .file records into the correct section	2014-05-02 17:45:24 +00:00
Disassembler	AArch64/ARM64: disable test directory if ARM64 not present	2014-05-07 10:42:06 +00:00
ELF	Fix pr19645.	2014-05-03 19:57:04 +00:00
MachO
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Mips	[mips] Add highly experimental support for MIPS-I, MIPS-II, MIPS-III, and MIPS-V	2014-05-07 16:25:22 +00:00
PowerPC
Sparc
SystemZ
X86