Chris Lattner df65de42cf Fix PR672 another way which should be more robust ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24585 91177308-0d34-0410-b5e6-96231b3b80d8		2005-12-04 06:03:50 +00:00
..
Alpha	major think-o	2005-12-01 17:48:51 +00:00
CBackend
IA64	IA64 doesn't support the LOCATION node, and for some reason the ISelPattern	2005-12-01 18:19:53 +00:00
PowerPC	Make sure these get added into the codegenmap when appropriate	2005-12-01 18:09:22 +00:00
Skeleton	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
Sparc	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
SparcV8	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
SparcV9	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
X86	Fix PR672 another way which should be more robust	2005-12-04 06:03:50 +00:00
Makefile
MRegisterInfo.cpp
SubtargetFeature.cpp
Target.td	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
TargetData.cpp
TargetFrameInfo.cpp
TargetInstrInfo.cpp
TargetMachine.cpp
TargetMachineRegistry.cpp
TargetSchedInfo.cpp
TargetSchedule.td
TargetSelectionDAG.td
TargetSubtarget.cpp