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https://github.com/c64scene-ar/llvm-6502.git
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fc22bfd921
This patch enables the vec_vsx_ld and vec_vsx_st intrinsics for PowerPC, which provide programmer access to the lxvd2x, lxvw4x, stxvd2x, and stxvw4x instructions. New LLVM intrinsics are provided to represent these four instructions in IntrinsicsPowerPC.td. These are patterned after the similar intrinsics for lvx and stvx (Altivec). In PPCInstrVSX.td, these intrinsics are tied to the code gen patterns, with additional patterns to allow plain vanilla loads and stores to still generate these instructions. At -O1 and higher the intrinsics are immediately converted to loads and stores in InstCombineCalls.cpp. This will open up more optimization opportunities while still allowing the correct instructions to be generated. (Similar code exists for aligned Altivec loads and stores.) The new intrinsics are added to the code that checks for consecutive loads and stores in PPCISelLowering.cpp, as well as to PPCTargetLowering::getTgtMemIntrinsic(). There's a new test to verify the correct instructions are generated. The loads and stores tend to be reordered, so the test just counts their number. It runs at -O2, as it's not very effective to test this at -O0, when many unnecessary loads and stores are generated. I ended up having to modify vsx-fma-m.ll. It turns out this test case is slightly unreliable, but I don't know a good way to prevent problems with it. The xvmaddmdp instructions read and write the same register, which is one of the multiplicands. Commutativity allows either to be chosen. If the FMAs are reordered differently than expected by the test, the register assignment can be different as a result. Hopefully this doesn't change often. There is a companion patch for Clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221767 91177308-0d34-0410-b5e6-96231b3b80d8
245 lines
9.5 KiB
LLVM
245 lines
9.5 KiB
LLVM
; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s
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; Also run with -schedule-ppc-vsx-fma-mutation-early as a stress test for the
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; live-interval-updating logic.
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; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx -schedule-ppc-vsx-fma-mutation-early
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define void @test1(double %a, double %b, double %c, double %e, double* nocapture %d) #0 {
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entry:
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%0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
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store double %0, double* %d, align 8
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%1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
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%arrayidx1 = getelementptr inbounds double* %d, i64 1
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store double %1, double* %arrayidx1, align 8
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ret void
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; CHECK-LABEL: @test1
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; CHECK-DAG: li [[C1:[0-9]+]], 8
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; CHECK-DAG: xsmaddmdp 3, 2, 1
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; CHECK-DAG: xsmaddadp 1, 2, 4
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; CHECK-DAG: stxsdx 3, 0, 7
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; CHECK-DAG: stxsdx 1, 7, [[C1]]
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; CHECK: blr
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}
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define void @test2(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 {
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entry:
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%0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
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store double %0, double* %d, align 8
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%1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
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%arrayidx1 = getelementptr inbounds double* %d, i64 1
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store double %1, double* %arrayidx1, align 8
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%2 = tail call double @llvm.fma.f64(double %b, double %f, double %a)
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%arrayidx2 = getelementptr inbounds double* %d, i64 2
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store double %2, double* %arrayidx2, align 8
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ret void
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; CHECK-LABEL: @test2
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; CHECK-DAG: li [[C1:[0-9]+]], 8
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; CHECK-DAG: li [[C2:[0-9]+]], 16
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; CHECK-DAG: xsmaddmdp 3, 2, 1
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; CHECK-DAG: xsmaddmdp 4, 2, 1
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; CHECK-DAG: xsmaddadp 1, 2, 5
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; CHECK-DAG: stxsdx 3, 0, 8
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; CHECK-DAG: stxsdx 4, 8, [[C1]]
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; CHECK-DAG: stxsdx 1, 8, [[C2]]
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; CHECK: blr
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}
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define void @test3(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 {
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entry:
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%0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
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store double %0, double* %d, align 8
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%1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
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%2 = tail call double @llvm.fma.f64(double %b, double %c, double %1)
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%arrayidx1 = getelementptr inbounds double* %d, i64 3
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store double %2, double* %arrayidx1, align 8
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%3 = tail call double @llvm.fma.f64(double %b, double %f, double %a)
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%arrayidx2 = getelementptr inbounds double* %d, i64 2
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store double %3, double* %arrayidx2, align 8
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%arrayidx3 = getelementptr inbounds double* %d, i64 1
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store double %1, double* %arrayidx3, align 8
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ret void
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; CHECK-LABEL: @test3
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; CHECK-DAG: fmr [[F1:[0-9]+]], 1
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; CHECK-DAG: li [[C1:[0-9]+]], 24
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; CHECK-DAG: li [[C2:[0-9]+]], 16
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; CHECK-DAG: li [[C3:[0-9]+]], 8
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; CHECK-DAG: xsmaddmdp 4, 2, 1
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; CHECK-DAG: xsmaddadp 1, 2, 5
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; Note: We could convert this next FMA to M-type as well, but it would require
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; re-ordering the instructions.
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; CHECK-DAG: xsmaddadp [[F1]], 2, 3
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; CHECK-DAG: xsmaddmdp 2, 3, 4
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; CHECK-DAG: stxsdx [[F1]], 0, 8
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; CHECK-DAG: stxsdx 2, 8, [[C1]]
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; CHECK-DAG: stxsdx 1, 8, [[C2]]
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; CHECK-DAG: stxsdx 4, 8, [[C3]]
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; CHECK: blr
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}
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define void @test4(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 {
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entry:
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%0 = tail call double @llvm.fma.f64(double %b, double %c, double %a)
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store double %0, double* %d, align 8
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%1 = tail call double @llvm.fma.f64(double %b, double %e, double %a)
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%arrayidx1 = getelementptr inbounds double* %d, i64 1
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store double %1, double* %arrayidx1, align 8
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%2 = tail call double @llvm.fma.f64(double %b, double %c, double %1)
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%arrayidx3 = getelementptr inbounds double* %d, i64 3
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store double %2, double* %arrayidx3, align 8
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%3 = tail call double @llvm.fma.f64(double %b, double %f, double %a)
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%arrayidx4 = getelementptr inbounds double* %d, i64 2
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store double %3, double* %arrayidx4, align 8
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ret void
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; CHECK-LABEL: @test4
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; CHECK-DAG: fmr [[F1:[0-9]+]], 1
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; CHECK-DAG: li [[C1:[0-9]+]], 8
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; CHECK-DAG: li [[C2:[0-9]+]], 16
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; CHECK-DAG: xsmaddmdp 4, 2, 1
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; Note: We could convert this next FMA to M-type as well, but it would require
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; re-ordering the instructions.
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; CHECK-DAG: xsmaddadp 1, 2, 5
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; CHECK-DAG: xsmaddadp [[F1]], 2, 3
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; CHECK-DAG: stxsdx [[F1]], 0, 8
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; CHECK-DAG: stxsdx 4, 8, [[C1]]
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; CHECK-DAG: li [[C3:[0-9]+]], 24
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; CHECK-DAG: xsmaddadp 4, 2, 3
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; CHECK-DAG: stxsdx 4, 8, [[C3]]
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; CHECK-DAG: stxsdx 1, 8, [[C2]]
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; CHECK: blr
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}
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declare double @llvm.fma.f64(double, double, double) #0
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define void @testv1(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double>* nocapture %d) #0 {
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entry:
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%0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)
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store <2 x double> %0, <2 x double>* %d, align 8
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%1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
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%arrayidx1 = getelementptr inbounds <2 x double>* %d, i64 1
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store <2 x double> %1, <2 x double>* %arrayidx1, align 8
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ret void
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; CHECK-LABEL: @testv1
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; CHECK-DAG: xvmaddmdp 36, 35, 34
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; CHECK-DAG: xvmaddadp 34, 35, 37
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; CHECK-DAG: li [[C1:[0-9]+]], 16
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; CHECK-DAG: stxvd2x 36, 0, 3
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; CHECK-DAG: stxvd2x 34, 3, [[C1:[0-9]+]]
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; CHECK: blr
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}
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define void @testv2(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 {
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entry:
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%0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)
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store <2 x double> %0, <2 x double>* %d, align 8
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%1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
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%arrayidx1 = getelementptr inbounds <2 x double>* %d, i64 1
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store <2 x double> %1, <2 x double>* %arrayidx1, align 8
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%2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)
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%arrayidx2 = getelementptr inbounds <2 x double>* %d, i64 2
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store <2 x double> %2, <2 x double>* %arrayidx2, align 8
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ret void
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; CHECK-LABEL: @testv2
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; CHECK-DAG: xvmaddmdp 36, 35, 34
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; CHECK-DAG: xvmaddmdp 37, 35, 34
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; CHECK-DAG: li [[C1:[0-9]+]], 16
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; CHECK-DAG: li [[C2:[0-9]+]], 32
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; CHECK-DAG: xvmaddadp 34, 35, 38
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; CHECK-DAG: stxvd2x 36, 0, 3
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; CHECK-DAG: stxvd2x 37, 3, [[C1:[0-9]+]]
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; CHECK-DAG: stxvd2x 34, 3, [[C2:[0-9]+]]
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; CHECK: blr
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}
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define void @testv3(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 {
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entry:
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%0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)
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store <2 x double> %0, <2 x double>* %d, align 8
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%1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
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%2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %1)
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%arrayidx1 = getelementptr inbounds <2 x double>* %d, i64 3
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store <2 x double> %2, <2 x double>* %arrayidx1, align 8
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%3 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)
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%arrayidx2 = getelementptr inbounds <2 x double>* %d, i64 2
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store <2 x double> %3, <2 x double>* %arrayidx2, align 8
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%arrayidx3 = getelementptr inbounds <2 x double>* %d, i64 1
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store <2 x double> %1, <2 x double>* %arrayidx3, align 8
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ret void
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; Note: There is some unavoidable changeability in this variant. If the
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; FMAs are reordered differently, the algorithm can pick a different
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; multiplicand to destroy, changing the register assignment. There isn't
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; a good way to express this possibility, so hopefully this doesn't change
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; too often.
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; CHECK-LABEL: @testv3
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; CHECK-DAG: xxlor [[V1:[0-9]+]], 34, 34
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; CHECK-DAG: li [[C1:[0-9]+]], 48
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; CHECK-DAG: li [[C2:[0-9]+]], 32
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; CHECK-DAG: xvmaddmdp 37, 35, 34
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; CHECK-DAG: li [[C3:[0-9]+]], 16
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; Note: We could convert this next FMA to M-type as well, but it would require
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; re-ordering the instructions.
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; CHECK-DAG: xvmaddadp [[V1]], 35, 36
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; CHECK-DAG: xvmaddmdp 36, 35, 37
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; CHECK-DAG: xvmaddadp 34, 35, 38
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; CHECK-DAG: stxvd2x 32, 0, 3
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; CHECK-DAG: stxvd2x 36, 3, [[C1]]
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; CHECK-DAG: stxvd2x 34, 3, [[C2]]
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; CHECK-DAG: stxvd2x 37, 3, [[C3]]
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; CHECK: blr
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}
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define void @testv4(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 {
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entry:
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%0 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %a)
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store <2 x double> %0, <2 x double>* %d, align 8
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%1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %e, <2 x double> %a)
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%arrayidx1 = getelementptr inbounds <2 x double>* %d, i64 1
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store <2 x double> %1, <2 x double>* %arrayidx1, align 8
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%2 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %c, <2 x double> %1)
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%arrayidx3 = getelementptr inbounds <2 x double>* %d, i64 3
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store <2 x double> %2, <2 x double>* %arrayidx3, align 8
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%3 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> %f, <2 x double> %a)
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%arrayidx4 = getelementptr inbounds <2 x double>* %d, i64 2
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store <2 x double> %3, <2 x double>* %arrayidx4, align 8
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ret void
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; CHECK-LABEL: @testv4
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; CHECK-DAG: xxlor [[V1:[0-9]+]], 34, 34
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; CHECK-DAG: xvmaddmdp 37, 35, 34
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; CHECK-DAG: li [[C1:[0-9]+]], 16
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; CHECK-DAG: li [[C2:[0-9]+]], 32
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; CHECK-DAG: xvmaddadp 34, 35, 38
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; Note: We could convert this next FMA to M-type as well, but it would require
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; re-ordering the instructions.
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; CHECK-DAG: xvmaddadp [[V1]], 35, 36
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; CHECK-DAG: stxvd2x 32, 0, 3
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; CHECK-DAG: stxvd2x 37, 3, [[C1]]
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; CHECK-DAG: li [[C3:[0-9]+]], 48
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; CHECK-DAG: xvmaddadp 37, 35, 36
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; CHECK-DAG: stxvd2x 37, 3, [[C3]]
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; CHECK-DAG: stxvd2x 34, 3, [[C2]]
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; CHECK: blr
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}
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declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) #0
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attributes #0 = { nounwind readnone }
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