mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
176 lines
6.7 KiB
LLVM
176 lines
6.7 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; SI-LABEL: {{^}}load_i8_to_f32:
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; SI: buffer_load_ubyte [[LOADREG:v[0-9]+]],
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; SI-NOT: bfe
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; SI-NOT: lshr
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; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]]
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; SI: buffer_store_dword [[CONV]],
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define void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
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%load = load i8 addrspace(1)* %in, align 1
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%cvt = uitofp i8 %load to float
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}load_v2i8_to_v2f32:
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; SI: buffer_load_ushort [[LOADREG:v[0-9]+]],
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; SI-NOT: bfe
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; SI-NOT: lshr
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; SI-NOT: and
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; SI-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]]
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; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]
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; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
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define void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <2 x i8> addrspace(1)* %in, align 1
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%cvt = uitofp <2 x i8> %load to <2 x float>
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store <2 x float> %cvt, <2 x float> addrspace(1)* %out, align 16
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ret void
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}
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; SI-LABEL: {{^}}load_v3i8_to_v3f32:
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; SI-NOT: bfe
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; SI-NOT: v_cvt_f32_ubyte3_e32
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; SI-DAG: v_cvt_f32_ubyte2_e32
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; SI-DAG: v_cvt_f32_ubyte1_e32
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; SI-DAG: v_cvt_f32_ubyte0_e32
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; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
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define void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <3 x i8> addrspace(1)* %in, align 1
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%cvt = uitofp <3 x i8> %load to <3 x float>
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store <3 x float> %cvt, <3 x float> addrspace(1)* %out, align 16
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ret void
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}
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; SI-LABEL: {{^}}load_v4i8_to_v4f32:
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; We can't use buffer_load_dword here, because the load is byte aligned, and
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; buffer_load_dword requires dword alignment.
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; SI: buffer_load_ushort
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; SI: buffer_load_ushort
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; SI: v_or_b32_e32 [[LOADREG:v[0-9]+]]
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; SI-NOT: bfe
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; SI-NOT: lshr
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; SI-DAG: v_cvt_f32_ubyte3_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]]
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; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[LOADREG]]
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; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, [[LOADREG]]
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; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]]
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; SI: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}},
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define void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <4 x i8> addrspace(1)* %in, align 1
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%cvt = uitofp <4 x i8> %load to <4 x float>
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store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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; XXX - This should really still be able to use the v_cvt_f32_ubyte0
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; for each component, but computeKnownBits doesn't handle vectors very
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; well.
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; SI-LABEL: {{^}}load_v4i8_to_v4f32_2_uses:
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; SI: v_cvt_f32_ubyte0_e32
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; SI: v_cvt_f32_ubyte0_e32
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; SI: v_cvt_f32_ubyte0_e32
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; SI: v_cvt_f32_ubyte0_e32
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; XXX - replace with this when v4i8 loads aren't scalarized anymore.
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; XSI: buffer_load_dword
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; XSI: v_cvt_f32_u32_e32
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; XSI: v_cvt_f32_u32_e32
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; XSI: v_cvt_f32_u32_e32
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; XSI: v_cvt_f32_u32_e32
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; SI: s_endpgm
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define void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <4 x i8> addrspace(1)* %in, align 4
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%cvt = uitofp <4 x i8> %load to <4 x float>
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store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
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%add = add <4 x i8> %load, <i8 9, i8 9, i8 9, i8 9> ; Second use of %load
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store <4 x i8> %add, <4 x i8> addrspace(1)* %out2, align 4
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ret void
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}
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; Make sure this doesn't crash.
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; SI-LABEL: {{^}}load_v7i8_to_v7f32:
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; SI: s_endpgm
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define void @load_v7i8_to_v7f32(<7 x float> addrspace(1)* noalias %out, <7 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <7 x i8> addrspace(1)* %in, align 1
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%cvt = uitofp <7 x i8> %load to <7 x float>
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store <7 x float> %cvt, <7 x float> addrspace(1)* %out, align 16
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ret void
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}
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; SI-LABEL: {{^}}load_v8i8_to_v8f32:
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; SI: buffer_load_dwordx2 v{{\[}}[[LOLOAD:[0-9]+]]:[[HILOAD:[0-9]+]]{{\]}},
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; SI-NOT: bfe
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; SI-NOT: lshr
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; SI-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[LOLOAD]]
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; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[LOLOAD]]
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; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[LOLOAD]]
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; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[LOLOAD]]
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; SI-DAG: v_cvt_f32_ubyte3_e32 v{{[0-9]+}}, v[[HILOAD]]
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; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, v[[HILOAD]]
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; SI-DAG: v_cvt_f32_ubyte1_e32 v{{[0-9]+}}, v[[HILOAD]]
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; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, v[[HILOAD]]
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; SI-NOT: bfe
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; SI-NOT: lshr
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; SI: buffer_store_dword
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; SI: buffer_store_dword
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; SI: buffer_store_dword
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; SI: buffer_store_dword
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; SI: buffer_store_dword
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; SI: buffer_store_dword
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; SI: buffer_store_dword
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; SI: buffer_store_dword
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define void @load_v8i8_to_v8f32(<8 x float> addrspace(1)* noalias %out, <8 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <8 x i8> addrspace(1)* %in, align 1
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%cvt = uitofp <8 x i8> %load to <8 x float>
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store <8 x float> %cvt, <8 x float> addrspace(1)* %out, align 16
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ret void
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}
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; SI-LABEL: {{^}}i8_zext_inreg_i32_to_f32:
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; SI: buffer_load_dword [[LOADREG:v[0-9]+]],
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; SI: v_add_i32_e32 [[ADD:v[0-9]+]], 2, [[LOADREG]]
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; SI-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]]
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; SI: buffer_store_dword [[CONV]],
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define void @i8_zext_inreg_i32_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
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%load = load i32 addrspace(1)* %in, align 4
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%add = add i32 %load, 2
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%inreg = and i32 %add, 255
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%cvt = uitofp i32 %inreg to float
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}i8_zext_inreg_hi1_to_f32:
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define void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind {
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%load = load i32 addrspace(1)* %in, align 4
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%inreg = and i32 %load, 65280
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%shr = lshr i32 %inreg, 8
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%cvt = uitofp i32 %shr to float
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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; We don't get these ones because of the zext, but instcombine removes
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; them so it shouldn't really matter.
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define void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind {
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%load = load i8 addrspace(1)* %in, align 1
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%ext = zext i8 %load to i32
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%cvt = uitofp i32 %ext to float
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store float %cvt, float addrspace(1)* %out, align 4
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ret void
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}
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define void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind {
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%load = load <4 x i8> addrspace(1)* %in, align 1
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%ext = zext <4 x i8> %load to <4 x i32>
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%cvt = uitofp <4 x i32> %ext to <4 x float>
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store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
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ret void
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}
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