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https://github.com/c64scene-ar/llvm-6502.git
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e7a8e298fb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221384 91177308-0d34-0410-b5e6-96231b3b80d8
35 lines
1.1 KiB
LLVM
35 lines
1.1 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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declare i32 @llvm.AMDGPU.imul24(i32, i32) nounwind readnone
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; FUNC-LABEL: {{^}}i32_mad24:
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; Signed 24-bit multiply is not supported on pre-Cayman GPUs.
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; EG: MULLO_INT
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; Make sure we aren't masking the inputs.
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; CM-NOT: AND
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; CM: MULADD_INT24
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; SI-NOT: and
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; SI: v_mad_i32_i24
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define void @i32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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entry:
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%0 = shl i32 %a, 8
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%a_24 = ashr i32 %0, 8
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%1 = shl i32 %b, 8
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%b_24 = ashr i32 %1, 8
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%2 = mul i32 %a_24, %b_24
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%3 = add i32 %2, %c
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: @test_imul24
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; SI: v_mad_i32_i24
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define void @test_imul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
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%mul = call i32 @llvm.AMDGPU.imul24(i32 %src0, i32 %src1) nounwind readnone
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%add = add i32 %mul, %src2
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store i32 %add, i32 addrspace(1)* %out, align 4
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ret void
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}
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