llvm-6502/lib/CodeGen
Lang Hames dfccd9ee98 Add missing case to switch statement - DAGTypeLegalizer::ExpandIntegerResult
should expand ATOMIC_CMP_SWAP nodes the same way that it does for ATOMIC_SWAP.

Since ATOMIC_LOADs on some targets (e.g. older ARM variants) get legalized to
ATOMIC_CMP_SWAPs, the missing case had been causing i64 atomic loads to crash
during isel.

<rdar://problem/14074644>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-28 18:36:42 +00:00
..
AsmPrinter Remove unused code. No functionality change. 2013-06-25 18:49:55 +00:00
SelectionDAG Add missing case to switch statement - DAGTypeLegalizer::ExpandIntegerResult 2013-06-28 18:36:42 +00:00
AggressiveAntiDepBreaker.cpp Simplify logic now that r182490 is in place. No functional change intended. 2013-05-22 23:17:36 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp Assert that the target provided hints are in the allocation order. 2013-02-19 18:41:01 +00:00
AllocationOrder.h
Analysis.cpp Only pass 'returned' to target-specific lowering code when the value of entire register is guaranteed to be preserved. 2013-04-30 22:49:28 +00:00
AntiDepBreaker.h
BasicTargetTransformInfo.cpp Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 2013-06-19 20:51:24 +00:00
BranchFolding.cpp Fix tail merging to assign the (more) correct BasicBlock when splitting. 2013-06-24 01:55:01 +00:00
BranchFolding.h Fix tail merging to assign the (more) correct BasicBlock when splitting. 2013-06-24 01:55:01 +00:00
CalcSpillWeights.cpp Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo. 2013-06-17 19:00:36 +00:00
CallingConvLower.cpp For ARM backend, fixed "byval" attribute support. 2013-05-05 07:48:36 +00:00
CMakeLists.txt Remove the old CodePlacementOpt pass. 2013-03-29 17:14:24 +00:00
CodeGen.cpp This patch breaks up Wrap.h so that it does not have to include all of 2013-05-01 20:59:00 +00:00
CriticalAntiDepBreaker.cpp Simplify logic now that r182490 is in place. No functional change intended. 2013-05-22 23:17:36 +00:00
CriticalAntiDepBreaker.h This patch addresses bug 15031. 2013-01-28 18:36:58 +00:00
DeadMachineInstructionElim.cpp Simplify logic now that r182490 is in place. No functional change intended. 2013-05-22 23:17:36 +00:00
DFAPacketizer.cpp
DwarfEHPrepare.cpp Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 2013-06-19 20:51:24 +00:00
EarlyIfConversion.cpp Allow MachineTraceMetrics to be used when the model has no resources. 2013-04-02 22:27:45 +00:00
EdgeBundles.cpp
ErlangGC.cpp Add a GC plugin for Erlang 2013-03-25 13:47:46 +00:00
ExecutionDepsFix.cpp Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. 2013-05-24 22:23:49 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp Re-apply r175688, with the changes suggested by Jakob in PR15320. 2013-02-21 22:16:43 +00:00
GCMetadata.cpp Fix GCMetadaPrinter::finishAssembly not executed, patch by Yiannis Tsiouris. 2013-02-19 16:51:44 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp
IfConversion.cpp Simplify logic now that r182490 is in place. No functional change intended. 2013-05-22 23:17:36 +00:00
InlineSpiller.cpp Update physreg live intervals during remat. 2013-06-21 18:33:26 +00:00
InterferenceCache.cpp
InterferenceCache.h
IntrinsicLowering.cpp Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen. 2013-05-21 14:37:16 +00:00
JITCodeEmitter.cpp
LatencyPriorityQueue.cpp
LexicalScopes.cpp Correct indentation for dumping LexicalScope. 2013-02-02 00:02:03 +00:00
LiveDebugVariables.cpp Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions 2013-06-16 20:34:15 +00:00
LiveDebugVariables.h Clean up LDV, no functionality change. 2013-02-13 20:23:48 +00:00
LiveInterval.cpp Fix PR16110: Handle DBG_VALUE in ConnectedVNInfoEqClasses::Distribute(). 2013-05-23 17:02:23 +00:00
LiveIntervalAnalysis.cpp Added -precompute-phys-liveness for testing LiveIntervals updates. 2013-06-21 18:33:23 +00:00
LiveIntervalUnion.cpp
LiveRangeCalc.cpp Copy single reaching defs directly into the LiveInterval. 2013-02-20 23:08:26 +00:00
LiveRangeCalc.h Copy single reaching defs directly into the LiveInterval. 2013-02-20 23:08:26 +00:00
LiveRangeEdit.cpp Prevent LiveRangeEdit from deleting bundled instructions. 2013-06-22 00:33:48 +00:00
LiveRegMatrix.cpp
LiveStackAnalysis.cpp
LiveVariables.cpp Simplify logic now that r182490 is in place. No functional change intended. 2013-05-22 22:26:05 +00:00
LLVMBuild.txt Extracted ObjCARC.cpp into its own library libLLVMObjCARCOpts in preparation for refactoring the ARC Optimizer. 2013-01-28 01:35:51 +00:00
LLVMTargetMachine.cpp Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 2013-06-19 20:51:24 +00:00
LocalStackSlotAllocation.cpp LocalStackSlotAllocation improvements 2013-04-30 20:04:37 +00:00
MachineBasicBlock.cpp Use pointers to the MCAsmInfo and MCRegInfo. 2013-06-18 07:20:20 +00:00
MachineBlockFrequencyInfo.cpp BlockFrequency: Bump up the entry frequency a bit. 2013-06-25 13:34:40 +00:00
MachineBlockPlacement.cpp Fix a defect in code-layout pass, improving Benchmarks/Olden/em3d/em3d by about 30% 2013-06-04 01:00:57 +00:00
MachineBranchProbabilityInfo.cpp
MachineCodeEmitter.cpp
MachineCopyPropagation.cpp Simplify logic now that r182490 is in place. No functional change intended. 2013-05-22 23:17:36 +00:00
MachineCSE.cpp
MachineDominators.cpp
MachineFunction.cpp Directly access objects which may change during compilation. 2013-06-17 20:41:25 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Debug Info: clean up usage of Verify. 2013-06-28 05:43:10 +00:00
MachineInstrBundle.cpp
MachineLICM.cpp
MachineLoopInfo.cpp
MachineModuleInfo.cpp Use pointers to the MCAsmInfo and MCRegInfo. 2013-06-18 07:20:20 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePostDominators.cpp Add a MachinePostDominator pass 2012-09-17 14:08:37 +00:00
MachineRegisterInfo.cpp Directly access objects which may change during compilation. 2013-06-17 20:41:25 +00:00
MachineScheduler.cpp MI-Sched: cleanup DEBUG output. 2013-06-21 18:33:01 +00:00
MachineSink.cpp
MachineSSAUpdater.cpp
MachineTraceMetrics.cpp Machine Model: Add MicroOpBufferSize and resource BufferSize. 2013-06-15 04:49:57 +00:00
MachineVerifier.cpp Simplify logic now that r182490 is in place. No functional change intended. 2013-05-22 23:17:36 +00:00
Makefile
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 2013-06-19 21:07:11 +00:00
PeepholeOptimizer.cpp
PHIElimination.cpp Don't rely on the isDead() MachineOperand flag when updating LiveIntervals. 2013-02-21 08:51:58 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp Simplify logic now that r182490 is in place. No functional change intended. 2013-05-22 23:17:36 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions 2013-06-16 20:34:15 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt Correct wrong register in this example, pointed out by Baoshan Pang. 2013-06-07 08:30:55 +00:00
RegAllocBase.cpp
RegAllocBase.h
RegAllocBasic.cpp Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo. 2013-06-17 19:00:36 +00:00
RegAllocFast.cpp Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions 2013-06-16 20:34:15 +00:00
RegAllocGreedy.cpp Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo. 2013-06-17 19:00:36 +00:00
RegAllocPBQP.cpp Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo. 2013-06-17 19:00:36 +00:00
RegisterClassInfo.cpp MI-Sched: Adjust regpressure limits for reserved regs. 2013-06-21 18:32:58 +00:00
RegisterCoalescer.cpp Fix a -join-globalcopies bug; handle undef operands. 2013-06-21 18:33:11 +00:00
RegisterCoalescer.h
RegisterPressure.cpp MI-Sched: Adjust regpressure limits for reserved regs. 2013-06-21 18:32:58 +00:00
RegisterScavenging.cpp Simplify logic now that r182490 is in place. No functional change intended. 2013-05-22 23:17:36 +00:00
ScheduleDAG.cpp Scheduler diagnostics. Print the register name. 2013-03-01 00:19:14 +00:00
ScheduleDAGInstrs.cpp Machine Model: Add MicroOpBufferSize and resource BufferSize. 2013-06-15 04:49:57 +00:00
ScheduleDAGPrinter.cpp ScheduleDAG: colorize the DOT graph and improve formatting. 2013-01-25 07:45:25 +00:00
ScoreboardHazardRecognizer.cpp
ShadowStackGC.cpp
ShrinkWrapping.cpp Add ArrayRef constructor from None, and do the cleanups that this constructor enables 2013-05-05 00:40:33 +00:00
SjLjEHPrepare.cpp Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 2013-06-19 20:51:24 +00:00
SlotIndexes.cpp Make some fixes for LiveInterval repair with debug info. Debug value 2013-02-23 10:25:25 +00:00
Spiller.cpp
Spiller.h
SpillPlacement.cpp Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo. 2013-06-17 19:00:36 +00:00
SpillPlacement.h
SplitKit.cpp Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo. 2013-06-17 19:00:36 +00:00
SplitKit.h Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo. 2013-06-17 19:00:36 +00:00
StackColoring.cpp Fix miscompile due to StackColoring incorrectly merging stack slots (PR15707) 2013-05-15 21:15:09 +00:00
StackProtector.cpp Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 2013-06-19 20:51:24 +00:00
StackSlotColoring.cpp Remove unused variable. 2013-06-27 11:26:41 +00:00
StrongPHIElimination.cpp
TailDuplication.cpp
TargetFrameLoweringImpl.cpp
TargetInstrInfo.cpp Machine Model: Add MicroOpBufferSize and resource BufferSize. 2013-06-15 04:49:57 +00:00
TargetLoweringBase.cpp Add LLVMContext argument to getSetCCResultType 2013-05-18 00:21:46 +00:00
TargetLoweringObjectFileImpl.cpp Micro-optimization 2013-04-26 21:15:08 +00:00
TargetOptionsImpl.cpp This is now a duplicate. 2013-06-19 22:16:33 +00:00
TargetRegisterInfo.cpp Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros. 2013-05-24 22:23:49 +00:00
TargetSchedule.cpp MI-Sched: handle ReadAdvance latencies as used by Swift. 2013-06-17 21:45:18 +00:00
TwoAddressInstructionPass.cpp TiedTo flag can now be placed on implicit operands. isTwoAddrUse() should look 2013-05-02 02:07:32 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.