6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-23 17:29:19 +00:00
Code Issues Projects Releases Wiki Activity
e03daa01f6
llvm-6502/test/CodeGen
History
Hans Wennborg e03daa01f6 [ARM] Use DWARF register numbers for CFI directives in ELF assembly 
It seems gas can't handle CFI directives with VFP register names ("d12", etc.).
This broke us trying to build Chromium for Android after 201423.

A gas bug has been filed: https://sourceware.org/bugzilla/show_bug.cgi?id=16694

compnerd suggested making this conditional on whether we're using the integrated
assembler or not. I'll look into that in a follow-up patch.

Differential Revision: http://llvm-reviews.chandlerc.com/D3049

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203635 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-12 03:52:34 +00:00
..
AArch64 IR: add a second ordering operand to cmpxhg for failure 2014-03-11 10:48:52 +00:00
ARM [ARM] Use DWARF register numbers for CFI directives in ELF assembly 2014-03-12 03:52:34 +00:00
CPP Begin adding docs and IR-level support for the inalloca attribute 2013-12-19 02:14:12 +00:00
Generic CommandLine: Exit successfully for -version and -help 2014-02-28 19:08:01 +00:00
Hexagon Fix broken CHECK lines 2014-02-16 07:31:05 +00:00
Inputs Debug Info: update testing cases to specify the debug info version number. 2013-11-22 21:49:45 +00:00
Mips IR: add a second ordering operand to cmpxhg for failure 2014-03-11 10:48:52 +00:00
MSP430 Fix known typos 2014-01-24 17:20:08 +00:00
NVPTX Followup to r203483 - add test. 2014-03-10 20:36:04 +00:00
PowerPC IR: add a second ordering operand to cmpxhg for failure 2014-03-11 10:48:52 +00:00
R600 R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCC 2014-03-07 20:12:39 +00:00
SPARC IR: add a second ordering operand to cmpxhg for failure 2014-03-11 10:48:52 +00:00
SystemZ IR: add a second ordering operand to cmpxhg for failure 2014-03-11 10:48:52 +00:00
Thumb Add triples to try to fix the windows bots. 2014-02-13 16:49:47 +00:00
Thumb2 ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block 2014-02-26 11:27:28 +00:00
X86 X86: Don't generate 64-bit movd after cmpneqsd in 32-bit mode (PR19059) 2014-03-11 15:49:24 +00:00
XCore [XCore] Add support for the "m" inline asm constraint. 2014-03-06 16:37:48 +00:00