Benjamin Kramer 6fac1fbf30 DAGCombiner: Fold a shuffle on CONCAT_VECTORS into a new CONCAT_VECTORS if possible. ... This pattern occurs in SROA output due to the way vector arguments are lowered on ARM. The testcase from PR15525 now compiles into this, which is better than the code we got with the old scalarrepl: _Store: ldr.w r9, [sp] vmov d17, r3, r9 vmov d16, r1, r2 vst1.8 {d16, d17}, [r0] bx lr Differential Revision: http://llvm-reviews.chandlerc.com/D647 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179106 91177308-0d34-0410-b5e6-96231b3b80d8		2013-04-09 17:41:43 +00:00
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AArch64	AArch64: remove barriers from AArch64 atomic operations.	2013-04-08 08:40:41 +00:00
ARM	DAGCombiner: Fold a shuffle on CONCAT_VECTORS into a new CONCAT_VECTORS if possible.	2013-04-09 17:41:43 +00:00
CPP
Generic
Hexagon
Inputs
MBlaze
Mips	[mips] Small update to the implementation of eh.return for Mips.	2013-04-02 23:02:07 +00:00
MSP430
NVPTX	[NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.	2013-03-30 14:29:30 +00:00
PowerPC	Use virtual base registers on PPC	2013-04-09 17:27:09 +00:00
R600	R600/SI: Add support for buffer stores v2	2013-04-05 23:31:51 +00:00
SI
SPARC	Compute correct frame sizes for SPARC v9 64-bit frames.	2013-04-09 04:37:47 +00:00
Thumb
Thumb2
X86	Make the test/CodeGen/X86/win32_sret.ll reliable on any CPU by explicitly specifying the -mcpu	2013-04-05 17:05:56 +00:00
XCore