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e179584f9b
llvm-6502/lib/Target/Alpha
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Nate Begeman e179584f9b Change how FP immediates are handled. 
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
   if it is legal.

This allows ConstantFP to be handled like Constant, allowing for 
targets that can encode FP immediates as MachineOperands.

As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants!  Hooray.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47121 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-14 08:57:00 +00:00
..
Alpha.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
Alpha.td Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
AlphaAsmPrinter.cpp Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
AlphaBranchSelector.cpp rename MachineInstr::setInstrDescriptor -> setDesc 2008-01-11 18:10:50 +00:00
AlphaCodeEmitter.cpp Change MachineRelocation::DoesntNeedFnStub to NeedStub. This fields will be used 2008-01-03 02:56:28 +00:00
AlphaInstrFormats.td rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 2008-01-06 23:38:27 +00:00
AlphaInstrInfo.cpp It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned. 2008-02-08 21:20:40 +00:00
AlphaInstrInfo.h Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
AlphaInstrInfo.td rename SDTRet -> SDTNone. 2008-01-15 22:02:54 +00:00
AlphaISelDAGToDAG.cpp Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. 2008-02-04 23:06:48 +00:00
AlphaISelLowering.cpp Change how FP immediates are handled. 2008-02-14 08:57:00 +00:00
AlphaISelLowering.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
AlphaJITInfo.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
AlphaJITInfo.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
AlphaLLRP.cpp Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm 2007-12-30 20:49:49 +00:00
AlphaRegisterInfo.cpp Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
AlphaRegisterInfo.h Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
AlphaRegisterInfo.td Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
AlphaRelocations.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
AlphaSchedule.td Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
AlphaSubtarget.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
AlphaSubtarget.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
AlphaTargetAsmInfo.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
AlphaTargetAsmInfo.h Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
AlphaTargetMachine.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
AlphaTargetMachine.h Rename MRegisterInfo to TargetRegisterInfo. 2008-02-10 18:45:23 +00:00
Makefile remove attribution from lib Makefiles. 2007-12-29 20:09:26 +00:00
README.txt Readme 2007-03-31 15:05:44 +00:00

README.txt 

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html