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https://github.com/c64scene-ar/llvm-6502.git
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13f4476c55
This saves us from having to copy a 64-bit 0 value into VGPRs for BUFFER_* instruction which only have a 12-bit immediate offset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215399 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
1.2 KiB
LLVM
41 lines
1.2 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
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; R600-CHECK: @test
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; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW
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; R600-CHECK: MEM_RAT_CACHELESS STORE_RAW
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; SI-CHECK: @test
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; SI-CHECK: S_MOV_B32 [[ZERO:s[0-9]]], 0{{$}}
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; SI-CHECK: V_MOV_B32_e32 v[[V_ZERO:[0-9]]], [[ZERO]]
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; SI-CHECK: BUFFER_STORE_DWORDX2 v[0:[[V_ZERO]]{{\]}}
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define void @test(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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entry:
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%0 = mul i32 %a, %b
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%1 = add i32 %0, %c
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%2 = zext i32 %1 to i64
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store i64 %2, i64 addrspace(1)* %out
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ret void
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}
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; SI-CHECK-LABEL: @testi1toi32
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; SI-CHECK: V_CNDMASK_B32
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define void @testi1toi32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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entry:
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%0 = icmp eq i32 %a, %b
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%1 = zext i1 %0 to i32
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; SI-CHECK-LABEL: @zext_i1_to_i64
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; SI-CHECK: V_CMP_EQ_I32
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; SI-CHECK: V_CNDMASK_B32
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; SI-CHECK: S_MOV_B32 s{{[0-9]+}}, 0
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define void @zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%cmp = icmp eq i32 %a, %b
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%ext = zext i1 %cmp to i64
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store i64 %ext, i64 addrspace(1)* %out, align 8
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ret void
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}
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