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https://github.com/c64scene-ar/llvm-6502.git
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0f3ac8d8d4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
226 lines
8.4 KiB
C++
226 lines
8.4 KiB
C++
//===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SPARC implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Sparc.h"
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#include "SparcRegisterInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/Type.h"
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#include "llvm/ADT/STLExtras.h"
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#include <iostream>
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using namespace llvm;
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SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
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: SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
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Subtarget(st) {
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}
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void SparcRegisterInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, int FI,
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const TargetRegisterClass *RC) const {
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// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
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if (RC == SP::IntRegsRegisterClass)
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BuildMI(MBB, I, SP::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
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else if (RC == SP::FPRegsRegisterClass)
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BuildMI(MBB, I, SP::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
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else if (RC == SP::DFPRegsRegisterClass)
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BuildMI(MBB, I, SP::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
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else
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assert(0 && "Can't store this register to stack slot");
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}
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void SparcRegisterInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const {
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if (RC == SP::IntRegsRegisterClass)
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BuildMI(MBB, I, SP::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
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else if (RC == SP::FPRegsRegisterClass)
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BuildMI(MBB, I, SP::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
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else if (RC == SP::DFPRegsRegisterClass)
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BuildMI(MBB, I, SP::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
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else
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assert(0 && "Can't load this register from stack slot");
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}
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void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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if (RC == SP::IntRegsRegisterClass)
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BuildMI(MBB, I, SP::ORrr, 2, DestReg).addReg(SP::G0).addReg(SrcReg);
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else if (RC == SP::FPRegsRegisterClass)
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BuildMI(MBB, I, SP::FMOVS, 1, DestReg).addReg(SrcReg);
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else if (RC == SP::DFPRegsRegisterClass)
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BuildMI(MBB, I, Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD,
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1, DestReg).addReg(SrcReg);
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else
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assert (0 && "Can't copy this register");
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}
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MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
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unsigned OpNum,
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int FI) const {
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bool isFloat = false;
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switch (MI->getOpcode()) {
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case SP::ORrr:
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if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
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MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
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if (OpNum == 0) // COPY -> STORE
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return BuildMI(SP::STri, 3).addFrameIndex(FI).addImm(0)
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.addReg(MI->getOperand(2).getReg());
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else // COPY -> LOAD
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return BuildMI(SP::LDri, 2, MI->getOperand(0).getReg())
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.addFrameIndex(FI).addImm(0);
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}
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break;
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case SP::FMOVS:
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isFloat = true;
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// FALLTHROUGH
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case SP::FMOVD:
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if (OpNum == 0) // COPY -> STORE
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return BuildMI(isFloat ? SP::STFri : SP::STDFri, 3)
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.addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
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else // COPY -> LOAD
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return BuildMI(isFloat ? SP::LDFri : SP::LDDFri, 2,
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MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
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break;
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}
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return 0;
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}
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const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {
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static const unsigned CalleeSaveRegs[] = { 0 };
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return CalleeSaveRegs;
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}
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const TargetRegisterClass* const*
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SparcRegisterInfo::getCalleeSaveRegClasses() const {
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static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
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return CalleeSaveRegClasses;
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}
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void SparcRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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MachineInstr &MI = *I;
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int Size = MI.getOperand(0).getImmedValue();
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if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
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Size = -Size;
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if (Size)
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BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addImm(Size);
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MBB.erase(I);
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}
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void
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SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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unsigned i = 0;
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MachineInstr &MI = *II;
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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// Addressable stack objects are accessed using neg. offsets from %fp
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MachineFunction &MF = *MI.getParent()->getParent();
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(i+1).getImmedValue();
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// Replace frame index with a frame pointer reference.
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if (Offset >= -4096 && Offset <= 4095) {
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// If the offset is small enough to fit in the immediate field, directly
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// encode it.
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MI.getOperand(i).ChangeToRegister(SP::I6);
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MI.getOperand(i+1).ChangeToImmediate(Offset);
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} else {
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// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
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// scavenge a register here instead of reserving G1 all of the time.
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unsigned OffHi = (unsigned)Offset >> 10U;
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BuildMI(*MI.getParent(), II, SP::SETHIi, 1, SP::G1).addImm(OffHi);
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// Emit G1 = G1 + I6
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BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
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SP::G1).addReg(SP::G1).addReg(SP::I6);
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// Insert: G1+%lo(offset) into the user.
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MI.getOperand(i).ChangeToRegister(SP::G1);
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MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
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}
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}
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void SparcRegisterInfo::
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processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
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void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Get the number of bytes to allocate from the FrameInfo
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int NumBytes = (int) MFI->getStackSize();
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// Emit the correct save instruction based on the number of bytes in
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// the frame. Minimum stack frame size according to V8 ABI is:
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// 16 words for register window spill
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// 1 word for address of returned aggregate-value
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// + 6 words for passing parameters on the stack
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// ----------
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// 23 words * 4 bytes per word = 92 bytes
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NumBytes += 92;
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// Round up to next doubleword boundary -- a double-word boundary
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// is required by the ABI.
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NumBytes = (NumBytes + 7) & ~7;
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NumBytes = -NumBytes;
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if (NumBytes >= -4096) {
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BuildMI(MBB, MBB.begin(), SP::SAVEri, 2,
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SP::O6).addImm(NumBytes).addReg(SP::O6);
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} else {
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MachineBasicBlock::iterator InsertPt = MBB.begin();
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// Emit this the hard way. This clobbers G1 which we always know is
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// available here.
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unsigned OffHi = (unsigned)NumBytes >> 10U;
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BuildMI(MBB, InsertPt, SP::SETHIi, 1, SP::G1).addImm(OffHi);
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// Emit G1 = G1 + I6
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BuildMI(MBB, InsertPt, SP::ORri, 2, SP::G1)
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.addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
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BuildMI(MBB, InsertPt, SP::SAVErr, 2,
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SP::O6).addReg(SP::O6).addReg(SP::G1);
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}
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}
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void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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assert(MBBI->getOpcode() == SP::RETL &&
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"Can only put epilog before 'retl' instruction!");
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BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
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}
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unsigned SparcRegisterInfo::getRARegister() const {
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assert(0 && "What is the return address register");
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return 0;
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}
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unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
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assert(0 && "What is the frame register");
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return SP::G1;
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}
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#include "SparcGenRegisterInfo.inc"
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