Vincent Lejeune 3ab0ba3cd8 R600: Factorize code handling Const Read Port limitation ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177078 91177308-0d34-0410-b5e6-96231b3b80d8		2013-03-14 15:50:45 +00:00
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AArch64	Test case hygiene.	2013-03-09 18:25:40 +00:00
ARM	Remove the unused 4th operand for DIFile debug info metadata	2013-03-13 22:05:21 +00:00
CPP	test commit: remove blank line.	2013-03-14 05:43:59 +00:00
Generic	For inline asm:	2013-01-11 18:12:39 +00:00
Hexagon	Hexagon: Add patterns for zero extended loads from i1->i64.	2013-03-08 14:15:15 +00:00
Inputs	Upgrading debug info test cases to be (more) compatible with the current debug info format.	2013-03-11 22:37:40 +00:00
MBlaze	Remove duplicate test contents.	2013-03-11 22:10:14 +00:00
Mips	Remove duplicate test contents.	2013-03-11 22:10:14 +00:00
MSP430	Remove duplicate test contents.	2013-03-11 22:10:14 +00:00
NVPTX	[NVPTX] Disable vector registers	2013-02-12 14:18:49 +00:00
PowerPC	Refactor filename/directory in DICompileUnit into a DIFile	2013-03-13 00:01:35 +00:00
R600	R600: Factorize code handling Const Read Port limitation	2013-03-14 15:50:45 +00:00
SI	Add R600 backend	2012-12-11 21:25:42 +00:00
SPARC	Remove duplicate test contents.	2013-03-11 22:10:14 +00:00
Thumb	Remove duplicate test contents.	2013-03-11 22:10:14 +00:00
Thumb2	SDAG: Handle scalarizing an extend of a <1 x iN> vector.	2013-03-07 05:47:54 +00:00
X86	Fix PR15309	2013-03-14 06:57:42 +00:00
XCore	Remove duplicate test contents.	2013-03-11 22:10:14 +00:00