llvm-6502/include/llvm/Target
Jakob Stoklund Olesen 4ce25d5d69 Add a RegisterTuples class to Target.td and TableGen.
A RegisterTuples instance is used to synthesize super-registers by
zipping together lists of sub-registers. This is useful for generating
pseudo-registers representing register sequence constraints like 'two
consecutive GPRs', or 'an even-odd pair of floating point registers'.

The RegisterTuples def can be used in register set operations when
building register classes. That is the only way of accessing the
synthesized super-registers.

For example, the ARM QQ register class of pseudo-registers could have
been formed like this:

  // Form pairs Q0_Q1, Q2_Q3, ...
  def QQPairs : RegisterTuples<[qsub_0, qsub_1],
                               [(decimate QPR, 2),
                                (decimate (shl QPR, 1), 2)]>;

  def QQ : RegisterClass<..., (add QQPairs)>;

Similarly, pseudo-registers representing '3 consecutive D-regs with
wraparound' look like:

  // Form D0_D1_D2, D1_D2_D3, ..., D30_D31_D0, D31_D0_D1.
  def DSeqTriples : RegisterTuples<[dsub_0, dsub_1, dsub_2],
                                   [(rotl DPR, 0),
                                    (rotl DPR, 1),
                                    (rotl DPR, 2)]>;

TableGen automatically computes aliasing information for the synthesized
registers.

Register tuples are still somewhat experimental. We still need to see
how they interact with MC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-20 02:50:54 +00:00
..
Mangler.h
SubtargetFeature.h
Target.td Add a RegisterTuples class to Target.td and TableGen. 2011-06-20 02:50:54 +00:00
TargetAsmBackend.h
TargetAsmInfo.h Use the dwarf->llvm mapping to print register names in the cfi 2011-05-30 20:20:15 +00:00
TargetAsmLexer.h
TargetAsmParser.h
TargetCallingConv.h
TargetCallingConv.td
TargetData.h
TargetELFWriterInfo.h
TargetFrameLowering.h
TargetInstrDesc.h
TargetInstrInfo.h
TargetInstrItineraries.h Initialize IssueWidth to zero. 2011-06-01 17:19:08 +00:00
TargetIntrinsicInfo.h
TargetJITInfo.h
TargetLibraryInfo.h add a copy ctor to TargetLibraryInfo. 2011-05-21 20:09:13 +00:00
TargetLowering.h Fix a bug in the type-lowering of integer-promoted elements. Add a check that 2011-06-17 20:54:12 +00:00
TargetLoweringObjectFile.h Add a parameter to the Win64 EH section getters to get a section with a 2011-05-27 19:09:24 +00:00
TargetMachine.h
TargetOpcodes.h Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand. This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change. 2011-06-16 18:17:13 +00:00
TargetOptions.h Replace the -unwind-tables option with a per function flag. This is more 2011-05-25 03:44:17 +00:00
TargetRegisterInfo.h Remove MethodProtos/MethodBodies and allocation_order_begin/end. 2011-06-18 03:08:20 +00:00
TargetRegistry.h Use the verbose asm flag instead of a new flag for decoding the LSDA. 2011-06-17 20:55:01 +00:00
TargetSchedule.td
TargetSelect.h
TargetSelectionDAG.td Add one more argument to the prefetch intrinsic to indicate whether it's a data 2011-06-14 04:58:37 +00:00
TargetSelectionDAGInfo.h
TargetSubtarget.h