llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-06 06:33:24 +00:00

History

Daniel Sanders 70f6f7ee3e [mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them

Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-III that was available in MIPS32

A small number of instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now.

There's some obvious InstAlias's that ought to be marked MIPS-III but arent.
This is because they are not currently tested. I intend to catch these with
a final pass through the tablegen records to find tablegen records without
ISA annotations.

Depends on D3674

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208408 91177308-0d34-0410-b5e6-96231b3b80d8

2014-05-09 13:02:27 +00:00

AArch64

AArch64/ARM64: add two more MC tests to ARM64 set.

2014-05-06 12:50:58 +00:00

ARM

test: fix silly typo

2014-05-08 01:41:04 +00:00

ARM64

AArch64/ARM64: make NEON vector list parsing a bit more robust

2014-05-06 12:50:51 +00:00

AsmParser

Integrated assbemler, macros: added 'vararg' argument qualifier support.