llvm-6502/test/CodeGen/ARM64/coalesce-ext.ll
Tim Northover 7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00

18 lines
613 B
LLVM

; RUN: llc -march=arm64 -mtriple=arm64-apple-darwin < %s | FileCheck %s
; Check that the peephole optimizer knows about sext and zext instructions.
; CHECK: test1sext
define i32 @test1sext(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
%C = add i64 %A, %B
; CHECK: add x[[SUM:[0-9]+]], x0, x1
%D = trunc i64 %C to i32
%E = shl i64 %C, 32
%F = ashr i64 %E, 32
; CHECK: sxtw x[[EXT:[0-9]+]], x[[SUM]]
store volatile i64 %F, i64 *%P2
; CHECK: str x[[EXT]]
store volatile i32 %D, i32* %P
; Reuse low bits of extended register, don't extend live range of SUM.
; CHECK: str w[[SUM]]
ret i32 %D
}