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<title>LLVM Atomic Instructions and Concurrency Guide</title>
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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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<link rel="stylesheet" href="llvm.css" type="text/css">
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<h1>
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LLVM Atomic Instructions and Concurrency Guide
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</h1>
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<ol>
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<li><a href="#introduction">Introduction</a></li>
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<li><a href="#loadstore">Load and store</a></li>
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<li><a href="#ordering">Atomic orderings</a></li>
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<li><a href="#otherinst">Other atomic instructions</a></li>
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<li><a href="#iropt">Atomics and IR optimization</a></li>
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<li><a href="#codegen">Atomics and Codegen</a></li>
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</ol>
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<div class="doc_author">
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<p>Written by Eli Friedman</p>
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</div>
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<!-- *********************************************************************** -->
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<h2>
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<a name="introduction">Introduction</a>
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</h2>
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<!-- *********************************************************************** -->
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<div>
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<p>Historically, LLVM has not had very strong support for concurrency; some
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minimal intrinsics were provided, and <code>volatile</code> was used in some
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cases to achieve rough semantics in the presence of concurrency. However, this
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is changing; there are now new instructions which are well-defined in the
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presence of threads and asynchronous signals, and the model for existing
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instructions has been clarified in the IR.</p>
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<p>The atomic instructions are designed specifically to provide readable IR and
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optimized code generation for the following:</p>
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<ul>
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<li>The new C++0x <code><atomic></code> header.</li>
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<li>Proper semantics for Java-style memory, for both <code>volatile</code> and
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regular shared variables.</li>
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<li>gcc-compatible <code>__sync_*</code> builtins.</li>
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<li>Other scenarios with atomic semantics, including <code>static</code>
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variables with non-trivial constructors in C++.</li>
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</ul>
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<p>This document is intended to provide a guide to anyone either writing a
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frontend for LLVM or working on optimization passes for LLVM with a guide
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for how to deal with instructions with special semantics in the presence of
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concurrency. This is not intended to be a precise guide to the semantics;
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the details can get extremely complicated and unreadable, and are not
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usually necessary.</p>
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</div>
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<!-- *********************************************************************** -->
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<h2>
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<a name="loadstore">Load and store</a>
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</h2>
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<!-- *********************************************************************** -->
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<div>
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<p>The basic <code>'load'</code> and <code>'store'</code> allow a variety of
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optimizations, but can have unintuitive results in a concurrent environment.
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For a frontend writer, the rule is essentially that all memory accessed
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with basic loads and stores by multiple threads should be protected by a
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lock or other synchronization; otherwise, you are likely to run into
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undefined behavior. (Do not use volatile as a substitute for atomics; it
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might work on some platforms, but does not provide the necessary guarantees
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in general.)</p>
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<p>From the optimizer's point of view, the rule is that if there
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are not any instructions with atomic ordering involved, concurrency does not
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matter, with one exception: if a variable might be visible to another
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thread or signal handler, a store cannot be inserted along a path where it
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might not execute otherwise. Note that speculative loads are allowed;
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a load which is part of a race returns <code>undef</code>, but is not
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undefined behavior.</p>
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<p>For cases where simple loads and stores are not sufficient, LLVM provides
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atomic loads and stores with varying levels of guarantees.</p>
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</div>
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<!-- *********************************************************************** -->
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<h2>
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<a name="ordering">Atomic orderings</a>
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</h2>
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<!-- *********************************************************************** -->
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<div>
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<p>In order to achieve a balance between performance and necessary guarantees,
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there are six levels of atomicity. They are listed in order of strength;
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each level includes all the guarantees of the previous level except for
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Acquire/Release.</p>
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<p>Unordered is the lowest level of atomicity. It essentially guarantees that
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races produce somewhat sane results instead of having undefined behavior.
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This is intended to match the Java memory model for shared variables. It
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cannot be used for synchronization, but is useful for Java and other
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"safe" languages which need to guarantee that the generated code never
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exhibits undefined behavior. Note that this guarantee is cheap on common
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platforms for loads of a native width, but can be expensive or unavailable
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for wider loads, like a 64-bit load on ARM. (A frontend for a "safe"
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language would normally split a 64-bit load on ARM into two 32-bit
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unordered loads.) In terms of the optimizer, this prohibits any
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transformation that transforms a single load into multiple loads,
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transforms a store into multiple stores, narrows a store, or stores a
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value which would not be stored otherwise. Some examples of unsafe
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optimizations are narrowing an assignment into a bitfield, rematerializing
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a load, and turning loads and stores into a memcpy call. Reordering
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unordered operations is safe, though, and optimizers should take
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advantage of that because unordered operations are common in
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languages that need them.</p>
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<p>Monotonic is the weakest level of atomicity that can be used in
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synchronization primitives, although it does not provide any general
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synchronization. It essentially guarantees that if you take all the
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operations affecting a specific address, a consistent ordering exists.
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This corresponds to the C++0x/C1x <code>memory_order_relaxed</code>; see
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those standards for the exact definition. If you are writing a frontend, do
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not use the low-level synchronization primitives unless you are compiling
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a language which requires it or are sure a given pattern is correct. In
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terms of the optimizer, this can be treated as a read+write on the relevant
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memory location (and alias analysis will take advantage of that). In
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addition, it is legal to reorder non-atomic and Unordered loads around
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Monotonic loads. CSE/DSE and a few other optimizations are allowed, but
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Monotonic operations are unlikely to be used in ways which would make
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those optimizations useful.</p>
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<p>Acquire provides a barrier of the sort necessary to acquire a lock to access
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other memory with normal loads and stores. This corresponds to the
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C++0x/C1x <code>memory_order_acquire</code>. It should also be used for
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C++0x/C1x <code>memory_order_consume</code>. This is a low-level
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synchronization primitive. In general, optimizers should treat this like
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a nothrow call.</p>
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<p>Release is similar to Acquire, but with a barrier of the sort necessary to
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release a lock. This corresponds to the C++0x/C1x
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<code>memory_order_release</code>. In general, optimizers should treat this
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like a nothrow call.</p>
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<p>AcquireRelease (<code>acq_rel</code> in IR) provides both an Acquire and a Release barrier.
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This corresponds to the C++0x/C1x <code>memory_order_acq_rel</code>. In general,
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optimizers should treat this like a nothrow call.</p>
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<p>SequentiallyConsistent (<code>seq_cst</code> in IR) provides Acquire and/or
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Release semantics, and in addition guarantees a total ordering exists with
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all other SequentiallyConsistent operations. This corresponds to the
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C++0x/C1x <code>memory_order_seq_cst</code>, and Java volatile. The intent
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of this ordering level is to provide a programming model which is relatively
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easy to understand. In general, optimizers should treat this like a
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nothrow call.</p>
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</div>
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<!-- *********************************************************************** -->
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<h2>
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<a name="otherinst">Other atomic instructions</a>
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</h2>
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<!-- *********************************************************************** -->
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<div>
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<p><code>cmpxchg</code> and <code>atomicrmw</code> are essentially like an
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atomic load followed by an atomic store (where the store is conditional for
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<code>cmpxchg</code>), but no other memory operation can happen between
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the load and store. Note that our cmpxchg does not have quite as many
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options for making cmpxchg weaker as the C++0x version.</p>
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<p>A <code>fence</code> provides Acquire and/or Release ordering which is not
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part of another operation; it is normally used along with Monotonic memory
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operations. A Monotonic load followed by an Acquire fence is roughly
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equivalent to an Acquire load.</p>
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<p>Frontends generating atomic instructions generally need to be aware of the
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target to some degree; atomic instructions are guaranteed to be lock-free,
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and therefore an instruction which is wider than the target natively supports
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can be impossible to generate.</p>
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</div>
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<!-- *********************************************************************** -->
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<h2>
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<a name="iropt">Atomics and IR optimization</a>
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</h2>
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<!-- *********************************************************************** -->
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<div>
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<p>Predicates for optimizer writers to query:
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<ul>
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<li>isSimple(): A load or store which is not volatile or atomic. This is
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what, for example, memcpyopt would check for operations it might
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transform.
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<li>isUnordered(): A load or store which is not volatile and at most
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Unordered. This would be checked, for example, by LICM before hoisting
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an operation.
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<li>mayReadFromMemory()/mayWriteToMemory(): Existing predicate, but note
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that they return true for any operation which is volatile or at least
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Monotonic.
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<li>Alias analysis: Note that AA will return ModRef for anything Acquire or
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Release, and for the address accessed by any Monotonic operation.
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</ul>
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<p>There are essentially two components to supporting atomic operations. The
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first is making sure to query isSimple() or isUnordered() instead
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of isVolatile() before transforming an operation. The other piece is
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making sure that a transform does not end up replacing, for example, an
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Unordered operation with a non-atomic operation. Most of the other
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necessary checks automatically fall out from existing predicates and
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alias analysis queries.</p>
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<p>Some examples of how optimizations interact with various kinds of atomic
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operations:
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<ul>
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<li>memcpyopt: An atomic operation cannot be optimized into part of a
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memcpy/memset, including unordered loads/stores. It can pull operations
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across some atomic operations.
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<li>LICM: Unordered loads/stores can be moved out of a loop. It just treats
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monotonic operations like a read+write to a memory location, and anything
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stricter than that like a nothrow call.
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<li>DSE: Unordered stores can be DSE'ed like normal stores. Monotonic stores
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can be DSE'ed in some cases, but it's tricky to reason about, and not
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especially important.
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<li>Folding a load: Any atomic load from a constant global can be
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constant-folded, because it cannot be observed. Similar reasoning allows
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scalarrepl with atomic loads and stores.
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</ul>
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</div>
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<!-- *********************************************************************** -->
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<h2>
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<a name="codegen">Atomics and Codegen</a>
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</h2>
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<!-- *********************************************************************** -->
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<div>
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<p>Atomic operations are represented in the SelectionDAG with
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<code>ATOMIC_*</code> opcodes. On architectures which use barrier
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instructions for all atomic ordering (like ARM), appropriate fences are
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split out as the DAG is built.</p>
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<p>The MachineMemOperand for all atomic operations is currently marked as
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volatile; this is not correct in the IR sense of volatile, but CodeGen
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handles anything marked volatile very conservatively. This should get
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fixed at some point.</p>
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<p>The implementation of atomics on LL/SC architectures (like ARM) is currently
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a bit of a mess; there is a lot of copy-pasted code across targets, and
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the representation is relatively unsuited to optimization (it would be nice
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to be able to optimize loops involving cmpxchg etc.).</p>
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<p>On x86, all atomic loads generate a <code>MOV</code>.
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SequentiallyConsistent stores generate an <code>XCHG</code>, other stores
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generate a <code>MOV</code>. SequentiallyConsistent fences generate an
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<code>MFENCE</code>, other fences do not cause any code to be generated.
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cmpxchg uses the <code>LOCK CMPXCHG</code> instruction.
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<code>atomicrmw xchg</code> uses <code>XCHG</code>,
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<code>atomicrmw add</code> and <code>atomicrmw sub</code> use
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<code>XADD</code>, and all other <code>atomicrmw</code> operations generate
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a loop with <code>LOCK CMPXCHG</code>. Depending on the users of the
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result, some <code>atomicrmw</code> operations can be translated into
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operations like <code>LOCK AND</code>, but that does not work in
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general.</p>
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<p>On ARM, MIPS, and many other RISC architectures, Acquire, Release, and
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SequentiallyConsistent semantics require barrier instructions
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for every such operation. Loads and stores generate normal instructions.
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<code>atomicrmw</code> and <code>cmpxchg</code> generate LL/SC loops.</p>
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</div>
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<!-- *********************************************************************** -->
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<hr>
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<address>
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<a href="http://llvm.org/">LLVM Compiler Infrastructure</a><br>
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Last modified: $Date: 2011-08-09 02:07:00 -0700 (Tue, 09 Aug 2011) $
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</address>
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