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Changes per Jeffrey's comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137243 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -138,14 +138,16 @@ instructions has been clarified in the IR.</p>
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those optimizations useful.</p>
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<p>Acquire provides a barrier of the sort necessary to acquire a lock to access
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other memory with normal loads and stores. This corresponds to the
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C++0x/C1x <code>memory_order_acquire</code>. This is a low-level
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other memory with normal loads and stores. This corresponds to the
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C++0x/C1x <code>memory_order_acquire</code>. It should also be used for
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C++0x/C1x <code>memory_order_consume</code>. This is a low-level
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synchronization primitive. In general, optimizers should treat this like
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a nothrow call.</p>
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<p>Release is similar to Acquire, but with a barrier of the sort necessary to
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release a lock.This corresponds to the C++0x/C1x
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<code>memory_order_release</code>.</p>
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release a lock. This corresponds to the C++0x/C1x
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<code>memory_order_release</code>. In general, optimizers should treat this
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like a nothrow call.</p>
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<p>AcquireRelease (<code>acq_rel</code> in IR) provides both an Acquire and a Release barrier.
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This corresponds to the C++0x/C1x <code>memory_order_acq_rel</code>. In general,
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@ -171,8 +173,9 @@ instructions has been clarified in the IR.</p>
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<p><code>cmpxchg</code> and <code>atomicrmw</code> are essentially like an
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atomic load followed by an atomic store (where the store is conditional for
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<code>cmpxchg</code>), but no other memory operation operation can happen
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between the load and store.</p>
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<code>cmpxchg</code>), but no other memory operation can happen between
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the load and store. Note that our cmpxchg does not have quite as many
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options for making cmpxchg weaker as the C++0x version.</p>
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<p>A <code>fence</code> provides Acquire and/or Release ordering which is not
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part of another operation; it is normally used along with Monotonic memory
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@ -203,7 +206,7 @@ instructions has been clarified in the IR.</p>
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Unordered. This would be checked, for example, by LICM before hoisting
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an operation.
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<li>mayReadFromMemory()/mayWriteToMemory(): Existing predicate, but note
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that they returns true for any operation which is volatile or at least
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that they return true for any operation which is volatile or at least
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Monotonic.
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<li>Alias analysis: Note that AA will return ModRef for anything Acquire or
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Release, and for the address accessed by any Monotonic operation.
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