Bruno Cardoso Lopes 3c8e1bee63 Support x86 "eiz" and "riz" pseudo index registers in the assembler. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109295 91177308-0d34-0410-b5e6-96231b3b80d8		2010-07-24 00:06:39 +00:00
..
dg.exp
x86_32-avx-clmul-encoding.s	Add AVX version of CLMUL instructions	2010-07-23 18:41:12 +00:00
x86_32-avx-encoding.s	Support x86 "eiz" and "riz" pseudo index registers in the assembler.	2010-07-24 00:06:39 +00:00
x86_32-bit_cat.s
x86_32-bit.s
x86_32-encoding.s	Support x86 "eiz" and "riz" pseudo index registers in the assembler.	2010-07-24 00:06:39 +00:00
x86_32-fma3-encoding.s	Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual	2010-07-23 00:54:35 +00:00
x86_32-mismatched-add.s
x86_32-new-encoder.s	X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same	2010-07-19 20:44:16 +00:00
x86_64-avx-clmul-encoding.s	Add AVX version of CLMUL instructions	2010-07-23 18:41:12 +00:00
x86_64-avx-encoding.s	Support x86 "eiz" and "riz" pseudo index registers in the assembler.	2010-07-24 00:06:39 +00:00
x86_64-encoding.s	Support x86 "eiz" and "riz" pseudo index registers in the assembler.	2010-07-24 00:06:39 +00:00
x86_64-fma3-encoding.s	Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual	2010-07-23 00:54:35 +00:00
x86_64-imm-widths.s
x86_64-incl_decl.s
x86_64-new-encoder.s	X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same	2010-07-19 20:44:16 +00:00
x86_64-operands.s
x86_64-suffix-matching.s
x86_instructions.s
x86_operands.s
x86_word_directive.s