llvm-6502/test/CodeGen
Bill Wendling e36b47e17b Revert r176154 in favor of a better approach.
Code generation makes some basic assumptions about the IR it's been given. In
particular, if there is only one 'invoke' in the function, then that invoke
won't be going away. However, with the advent of the `llvm.donothing' intrinsic,
those invokes may go away. If all of them go away, the landing pad no longer has
any users. This confuses the back-end, which asserts.

This happens with SjLj exceptions, because that's the model that modifies the IR
based on there being invokes, etc. in the function.

Remove any invokes of `llvm.donothing' during SjLj EH preparation. This will
give us a CFG that the back-end won't be confused about. If all of the invokes
in a function are removed, then the SjLj EH prepare pass won't insert the bogus
code the relies upon the invokes being there.
<rdar://problem/13228754&13316637>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176677 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-08 02:21:08 +00:00
..
AArch64 AArch64: be more careful resorting to inefficient addressing for weak vars. 2013-02-28 14:36:31 +00:00
ARM Revert r176154 in favor of a better approach. 2013-03-08 02:21:08 +00:00
CPP
Generic For inline asm: 2013-01-11 18:12:39 +00:00
Hexagon Hexagon: Handle i8, i16 and i1 Var Args. 2013-03-07 20:28:34 +00:00
MBlaze
Mips [mips] Custom-legalize BR_JT. 2013-03-06 21:32:03 +00:00
MSP430
NVPTX [NVPTX] Disable vector registers 2013-02-12 14:18:49 +00:00
PowerPC Fix PR15332 (patch by Florian Zeitz). 2013-02-26 21:28:57 +00:00
R600 R600: Turn BUILD_VECTOR into Reg_Sequence 2013-03-05 15:04:49 +00:00
SI
SPARC
Thumb llvm/test/CodeGen/Thumb/iabs.ll: Add explicit -mtriple=thumb-unknown-unknown to appease win32 hosts. 2013-03-05 02:18:52 +00:00
Thumb2 SDAG: Handle scalarizing an extend of a <1 x iN> vector. 2013-03-07 05:47:54 +00:00
X86 Upgrade tests to the latest debug info format. 2013-03-08 00:23:31 +00:00
XCore