mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
102 lines
6.1 KiB
LLVM
102 lines
6.1 KiB
LLVM
; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs
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; PR11829
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
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target triple = "armv7-none-linux-gnueabi"
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define arm_aapcs_vfpcc void @foo(i8* nocapture %arg) nounwind uwtable align 2 {
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bb:
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br i1 undef, label %bb1, label %bb2
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bb1: ; preds = %bb
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unreachable
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bb2: ; preds = %bb
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br label %bb3
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bb3: ; preds = %bb4, %bb2
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%tmp = icmp slt i32 undef, undef
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br i1 %tmp, label %bb4, label %bb67
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bb4: ; preds = %bb3
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%tmp5 = load <4 x i32>, <4 x i32>* undef, align 16
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%tmp6 = and <4 x i32> %tmp5, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>
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%tmp7 = or <4 x i32> %tmp6, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
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%tmp8 = bitcast <4 x i32> %tmp7 to <4 x float>
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%tmp9 = fsub <4 x float> %tmp8, bitcast (i128 or (i128 shl (i128 zext (i64 trunc (i128 lshr (i128 bitcast (<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i128), i128 64) to i64) to i128), i128 64), i128 zext (i64 trunc (i128 bitcast (<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i128) to i64) to i128)) to <4 x float>)
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%tmp10 = fmul <4 x float> undef, %tmp9
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%tmp11 = fadd <4 x float> undef, %tmp10
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%tmp12 = bitcast <4 x float> zeroinitializer to i128
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%tmp13 = lshr i128 %tmp12, 64
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%tmp14 = trunc i128 %tmp13 to i64
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%tmp15 = insertvalue [2 x i64] undef, i64 %tmp14, 1
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%tmp16 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp11) nounwind
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%tmp17 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp16, <4 x float> %tmp11) nounwind
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%tmp18 = fmul <4 x float> %tmp17, %tmp16
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%tmp19 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp18, <4 x float> %tmp11) nounwind
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%tmp20 = fmul <4 x float> %tmp19, %tmp18
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%tmp21 = fmul <4 x float> %tmp20, zeroinitializer
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%tmp22 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp21, <4 x float> undef) nounwind
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call arm_aapcs_vfpcc void @bar(i8* null, i8* undef, <4 x i32>* undef, [2 x i64] zeroinitializer) nounwind
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%tmp23 = bitcast <4 x float> %tmp22 to i128
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%tmp24 = trunc i128 %tmp23 to i64
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%tmp25 = insertvalue [2 x i64] undef, i64 %tmp24, 0
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%tmp26 = insertvalue [2 x i64] %tmp25, i64 0, 1
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%tmp27 = load float, float* undef, align 4
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%tmp28 = insertelement <4 x float> undef, float %tmp27, i32 3
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%tmp29 = load <4 x i32>, <4 x i32>* undef, align 16
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%tmp30 = and <4 x i32> %tmp29, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>
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%tmp31 = or <4 x i32> %tmp30, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
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%tmp32 = bitcast <4 x i32> %tmp31 to <4 x float>
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%tmp33 = fsub <4 x float> %tmp32, bitcast (i128 or (i128 shl (i128 zext (i64 trunc (i128 lshr (i128 bitcast (<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i128), i128 64) to i64) to i128), i128 64), i128 zext (i64 trunc (i128 bitcast (<4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> to i128) to i64) to i128)) to <4 x float>)
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%tmp34 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> undef, <4 x float> %tmp28) nounwind
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%tmp35 = fmul <4 x float> %tmp34, undef
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%tmp36 = fmul <4 x float> %tmp35, undef
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%tmp37 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind
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%tmp38 = load float, float* undef, align 4
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%tmp39 = insertelement <2 x float> undef, float %tmp38, i32 0
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%tmp40 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind
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%tmp41 = load float, float* undef, align 4
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%tmp42 = insertelement <4 x float> undef, float %tmp41, i32 3
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%tmp43 = shufflevector <2 x float> %tmp39, <2 x float> undef, <4 x i32> zeroinitializer
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%tmp44 = fmul <4 x float> %tmp33, %tmp43
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%tmp45 = fadd <4 x float> %tmp42, %tmp44
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%tmp46 = fsub <4 x float> %tmp45, undef
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%tmp47 = fmul <4 x float> %tmp46, %tmp36
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%tmp48 = fadd <4 x float> undef, %tmp47
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%tmp49 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind
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%tmp50 = load float, float* undef, align 4
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%tmp51 = insertelement <4 x float> undef, float %tmp50, i32 3
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%tmp52 = call arm_aapcs_vfpcc float* null(i8* undef) nounwind
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%tmp54 = load float, float* %tmp52, align 4
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%tmp55 = insertelement <4 x float> undef, float %tmp54, i32 3
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%tmp56 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp22
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%tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind
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%tmp58 = fmul <4 x float> undef, %tmp57
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%tmp59 = fsub <4 x float> %tmp51, %tmp48
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%tmp60 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp58
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%tmp61 = fmul <4 x float> %tmp59, %tmp60
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%tmp62 = fadd <4 x float> %tmp48, %tmp61
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call arm_aapcs_vfpcc void @baz(i8* undef, i8* undef, [2 x i64] %tmp26, <4 x i32>* undef)
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%tmp63 = bitcast <4 x float> %tmp62 to i128
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%tmp64 = lshr i128 %tmp63, 64
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%tmp65 = trunc i128 %tmp64 to i64
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%tmp66 = insertvalue [2 x i64] zeroinitializer, i64 %tmp65, 1
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call arm_aapcs_vfpcc void @quux(i8* undef, i8* undef, [2 x i64] undef, i8* undef, [2 x i64] %tmp66, i8* undef, i8* undef, [2 x i64] %tmp26, [2 x i64] %tmp15, <4 x i32>* undef)
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br label %bb3
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bb67: ; preds = %bb3
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ret void
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}
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declare arm_aapcs_vfpcc void @bar(i8*, i8*, <4 x i32>*, [2 x i64])
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declare arm_aapcs_vfpcc void @baz(i8*, i8* nocapture, [2 x i64], <4 x i32>* nocapture) nounwind uwtable inlinehint align 2
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declare arm_aapcs_vfpcc void @quux(i8*, i8*, [2 x i64], i8* nocapture, [2 x i64], i8* nocapture, i8* nocapture, [2 x i64], [2 x i64], <4 x i32>* nocapture) nounwind uwtable inlinehint align 2
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declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
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