John Brawn e38f45effc [ARM] Use AEABI aligned function variants ...

AEABI defines aligned variants of memcpy etc. that can be faster than
the default version due to not having to do alignment checks. When
emitting target code for these functions make use of these aligned
variants if possible. Also convert memset to memclr if possible.

Differential Revision: http://reviews.llvm.org/D8060


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237127 91177308-0d34-0410-b5e6-96231b3b80d8

2015-05-12 13:13:38 +00:00

..

AArch64

llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll: s/REQUIRE/REQUIRES/

2015-05-09 05:59:00 +00:00

ARM

[ARM] Use AEABI aligned function variants

2015-05-12 13:13:38 +00:00

BPF

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CPP

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Generic

Migrate existing backends that care about software floating point

2015-05-12 01:26:05 +00:00

Hexagon

[Hexagon] Generate more hardware loops

2015-05-08 20:18:21 +00:00

Inputs

IR: Give 'DI' prefix to debug info metadata

2015-04-29 16:38:44 +00:00

Mips

[mips][FastISel] Handle calls with non legal types i8 and i16.

2015-05-12 12:29:17 +00:00

MSP430

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NVPTX

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PowerPC

Fix test added in r236850 for OSX builders.

2015-05-08 14:04:54 +00:00

R600

R600/SI: Add VCC as an implict def of SI_KILL

2015-05-01 03:44:09 +00:00

SPARC

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SystemZ

[DAGCombiner] Account for getVectorIdxTy() when narrowing vector load

2015-05-05 19:34:10 +00:00

Thumb

IR: Give 'DI' prefix to debug info metadata

2015-04-29 16:38:44 +00:00

Thumb2

Thumb2SizeReduction: Check the correct set of registers for LDMIA.

2015-05-05 20:07:10 +00:00

WinEH

[WinEH] Handle nested landing pads that return directly to the parent function.

2015-05-11 23:06:02 +00:00

X86

Reverse ordering of base and derived pointer during safepoint lowering.

2015-05-12 13:12:14 +00:00

XCore

IR: Give 'DI' prefix to debug info metadata

2015-04-29 16:38:44 +00:00