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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
28 lines
850 B
LLVM
28 lines
850 B
LLVM
; RUN: llc -mtriple thumbv7--windows-itanium -code-model large -filetype obj -o - %s \
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; RUN: | llvm-objdump -no-show-raw-insn -d - | FileCheck %s
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; ModuleID = 'reduced.c'
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target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv7--windows-itanium"
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define arm_aapcs_vfpcc i8 @isel(i32 %i) {
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entry:
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%i.addr = alloca i32, align 4
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%buffer = alloca [4096 x i8], align 1
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store i32 %i, i32* %i.addr, align 4
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%0 = load i32, i32* %i.addr, align 4
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%rem = urem i32 %0, 4096
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%arrayidx = getelementptr inbounds [4096 x i8], [4096 x i8]* %buffer, i32 0, i32 %rem
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%1 = load volatile i8, i8* %arrayidx, align 1
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ret i8 %1
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}
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; CHECK-LABEL: isel
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; CHECK: push {r4, r5}
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; CHECK: movw r4, #{{\d*}}
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; CHECK: movw r12, #0
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; CHECK: movt r12, #0
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; CHECK: blx r12
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; CHECK: sub.w sp, sp, r4
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