mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-20 10:30:03 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
170 lines
6.7 KiB
LLVM
170 lines
6.7 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
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;CHECK-LABEL: vqshrns8:
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;CHECK: vqshrn.s16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: vqshrns16:
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;CHECK: vqshrn.s32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
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;CHECK-LABEL: vqshrns32:
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;CHECK: vqshrn.s64
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%tmp1 = load <2 x i64>, <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
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ret <2 x i32> %tmp2
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}
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define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
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;CHECK-LABEL: vqshrnu8:
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;CHECK: vqshrn.u16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: vqshrnu16:
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;CHECK: vqshrn.u32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
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;CHECK-LABEL: vqshrnu32:
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;CHECK: vqshrn.u64
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%tmp1 = load <2 x i64>, <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
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ret <2 x i32> %tmp2
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}
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define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
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;CHECK-LABEL: vqshruns8:
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;CHECK: vqshrun.s16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: vqshruns16:
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;CHECK: vqshrun.s32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind {
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;CHECK-LABEL: vqshruns32:
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;CHECK: vqshrun.s64
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%tmp1 = load <2 x i64>, <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
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ret <2 x i32> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
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define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
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;CHECK-LABEL: vqrshrns8:
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;CHECK: vqrshrn.s16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: vqrshrns16:
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;CHECK: vqrshrn.s32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
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;CHECK-LABEL: vqrshrns32:
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;CHECK: vqrshrn.s64
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%tmp1 = load <2 x i64>, <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
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ret <2 x i32> %tmp2
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}
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define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
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;CHECK-LABEL: vqrshrnu8:
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;CHECK: vqrshrn.u16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: vqrshrnu16:
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;CHECK: vqrshrn.u32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
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;CHECK-LABEL: vqrshrnu32:
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;CHECK: vqrshrn.u64
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%tmp1 = load <2 x i64>, <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
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ret <2 x i32> %tmp2
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}
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define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
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;CHECK-LABEL: vqrshruns8:
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;CHECK: vqrshrun.s16
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%tmp1 = load <8 x i16>, <8 x i16>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: vqrshruns16:
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;CHECK: vqrshrun.s32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind {
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;CHECK-LABEL: vqrshruns32:
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;CHECK: vqrshrun.s64
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%tmp1 = load <2 x i64>, <2 x i64>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
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ret <2 x i32> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
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