Matthias Braun da74817c50 Introduce ad hoc liveness tracking utility: LiveRegUnits ...

Contains a set of live register (units) and code to move forward and
backward in the schedule while updating the live set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192481 91177308-0d34-0410-b5e6-96231b3b80d8

2013-10-11 19:04:35 +00:00

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PBQP

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Analysis.h

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AsmPrinter.h

Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom comments for implicit defs

2013-10-11 12:39:36 +00:00

CalcSpillWeights.h

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CallingConvLower.h

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CommandFlags.h

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DAGCombine.h

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DFAPacketizer.h

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EdgeBundles.h

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FastISel.h

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FunctionLoweringInfo.h

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GCMetadata.h

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GCMetadataPrinter.h

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GCs.h

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GCStrategy.h

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IntrinsicLowering.h

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ISDOpcodes.h

[ARM] Use the load-acquire/store-release instructions optimally in AArch32.

2013-09-26 12:22:36 +00:00

JITCodeEmitter.h

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LatencyPriorityQueue.h

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LexicalScopes.h

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LinkAllAsmWriterComponents.h

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LinkAllCodegenComponents.h

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LiveInterval.h

Print register in LiveInterval::print()

2013-10-10 21:29:05 +00:00

LiveIntervalAnalysis.h

Represent RegUnit liveness with LiveRange instance

2013-10-10 21:29:02 +00:00

LiveIntervalUnion.h

Rename LiveRange to LiveInterval::Segment

2013-10-10 21:28:43 +00:00

LiveRangeEdit.h

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LiveRegMatrix.h

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LiveRegUnits.h

Introduce ad hoc liveness tracking utility: LiveRegUnits

2013-10-11 19:04:35 +00:00

LiveStackAnalysis.h

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LiveVariables.h

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MachineBasicBlock.h

Even more spelling fixes for "instruction".

2013-09-28 13:42:22 +00:00

MachineBlockFrequencyInfo.h

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MachineBranchProbabilityInfo.h

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MachineCodeEmitter.h

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MachineCodeInfo.h

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MachineConstantPool.h

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MachineDominators.h

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MachineFrameInfo.h

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MachineFunction.h

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MachineFunctionAnalysis.h

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MachineFunctionPass.h

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MachineInstr.h

Rename parameter: defined regs are not incoming.

2013-10-10 21:28:38 +00:00

MachineInstrBuilder.h

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MachineInstrBundle.h

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MachineJumpTableInfo.h

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MachineLoopInfo.h

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MachineMemOperand.h

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MachineModuleInfo.h

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MachineModuleInfoImpls.h

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MachineOperand.h

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MachinePassRegistry.h

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MachinePostDominators.h

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MachineRegisterInfo.h

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MachineRelocation.h

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MachineScheduler.h

Allow subtarget selection of the default MachineScheduler and document the interface.

2013-09-20 05:14:41 +00:00

MachineSSAUpdater.h

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MachineTraceMetrics.h

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MachORelocation.h

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Passes.h

Allow subtarget selection of the default MachineScheduler and document the interface.

2013-09-20 05:14:41 +00:00

PseudoSourceValue.h

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RegAllocPBQP.h

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RegAllocRegistry.h

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RegisterClassInfo.h

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RegisterPressure.h

Represent RegUnit liveness with LiveRange instance

2013-10-10 21:29:02 +00:00

RegisterScavenging.h

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ResourcePriorityQueue.h

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RuntimeLibcalls.h

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ScheduleDAG.h

Explicitly request unsigned enum types when desired

2013-10-08 20:15:11 +00:00

ScheduleDAGInstrs.h

Even more spelling fixes for "instruction".

2013-09-28 13:42:22 +00:00

ScheduleDFS.h

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ScheduleHazardRecognizer.h

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SchedulerRegistry.h

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ScoreboardHazardRecognizer.h

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SelectionDAG.h

[ARM] Use the load-acquire/store-release instructions optimally in AArch32.

2013-09-26 12:22:36 +00:00

SelectionDAGISel.h

Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon.

2013-10-05 05:38:16 +00:00

SelectionDAGNodes.h

Remove an old workaround for a compiler that EOL'd years ago.

2013-09-29 19:39:02 +00:00

SlotIndexes.h

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StackProtector.h

[stackprotector] Refactor the StackProtector pass from a single .cpp file into StackProtector.h and StackProtector.cpp.

2013-09-27 21:58:43 +00:00

TargetLoweringObjectFileImpl.h

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TargetSchedule.h

IfConverter: Use TargetSchedule for instruction latencies

2013-09-30 15:28:56 +00:00

ValueTypes.h

Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).

2013-10-10 17:00:52 +00:00

ValueTypes.td

Implement aarch64 neon instruction set AdvSIMD (Across).

2013-10-05 08:22:10 +00:00

VirtRegMap.h

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