llvm-6502/test/MC
Hal Finkel 100eab89f5 [PowerPC] Support register name prefixes for vector registers
Match binutils by supporting the optional register name prefix for new vector
registers ("vs" for VSX registers and "q" for QPX registers).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235665 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-23 23:16:22 +00:00
..
AArch64 [AArch64] LORID_EL1 register must be treated as read-only 2015-04-20 16:54:37 +00:00
ARM ARM: When spilling extra registers for alignment, prefer low registers on all Thumb targets. 2015-04-23 20:31:26 +00:00
AsmParser Add support for .ifnes psuedo-op. 2015-03-18 14:20:54 +00:00
COFF Add a proper fix for pr23025. 2015-04-17 11:27:13 +00:00
Disassembler [PowerPC] Use sync inst alias when printing 2015-04-23 23:05:08 +00:00
ELF Look past locals in comdats. 2015-04-20 12:44:06 +00:00
Hexagon Expand MUX instructions early on Hexagon 2015-03-31 13:35:12 +00:00
MachO MC: For variable symbols, maintain MCSymbol::Section as a cache. 2015-04-03 01:46:11 +00:00
Markup
Mips [mips] [IAS] Implement the .asciiz directive. 2015-04-21 11:50:52 +00:00
PowerPC [PowerPC] Support register name prefixes for vector registers 2015-04-23 23:16:22 +00:00
R600 R600/SI: Add missing -mcpu=SI to assembler test 2015-04-23 19:33:55 +00:00
Sparc Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00
SystemZ [SystemZ] Support transactional execution on zEC12 2015-04-01 12:51:43 +00:00
X86 AVX-512: Added VPMOVx2M instructions for SKX, 2015-04-21 14:38:31 +00:00