Justin Holewinski e459c0bf65 [NVPTX] Add NVPTXLowerStructArgs pass ... This works around the limitation that PTX does not allow .param space loads/stores with arbitrary pointers. If a function has a by-val struct ptr arg, say foo(%struct.x *byval %d), then add the following instructions to the first basic block : %temp = alloca %struct.x, align 8 %tt1 = bitcast %struct.x * %d to i8 * %tt2 = llvm.nvvm.cvt.gen.to.param %tt2 %tempd = bitcast i8 addrspace(101) * to %struct.x addrspace(101) * %tv = load %struct.x addrspace(101) * %tempd store %struct.x %tv, %struct.x * %temp, align 8 The above code allocates some space in the stack and copies the incoming struct from param space to local space. Then replace all occurences of %d by %temp. Fixes PR21465. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221377 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-05 18:19:30 +00:00
..
AArch64	[AArch64] Use the correct register class for ORR.	2014-11-04 22:20:07 +00:00
ARM	ARM: try to add extra CS-register whenever stack alignment >= 8.	2014-11-05 00:27:20 +00:00
CPP
Generic
Hexagon	Handle ctor/init_array initialization.	2014-11-03 14:56:05 +00:00
Inputs
Mips	ps][microMIPS] Implement CodeGen support for ANDI16 instruction	2014-11-05 17:43:00 +00:00
MSP430
NVPTX	[NVPTX] Add NVPTXLowerStructArgs pass	2014-11-05 18:19:30 +00:00
PowerPC	[PowerPC] Initial VSX intrinsic support, with min/max for vector double	2014-10-31 19:19:07 +00:00
R600	R600/SI: Change all instruction assembly names to lowercase.	2014-11-05 14:50:53 +00:00
SPARC
SystemZ
Thumb	Improve logic that decides if its profitable to commute when some of the virtual registers involved have uses/defs chains connecting them to physical register. Fix up the tests that this change improves.	2014-11-05 06:43:02 +00:00
Thumb2
X86	[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks.	2014-11-05 13:04:14 +00:00
XCore