llvm-6502/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp at e51a69c8fdcecf895ac0dff22bc2a8a779bd94de

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2026-03-12 05:42:47 +00:00

Files

Chris Lattner a81556fb52 teach SimplifyDemandedBits that exact shifts demand the bits they

are shifting out since they do require them to be zeros.  Similarly
for NUW/NSW bits of shl


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125263 91177308-0d34-0410-b5e6-96231b3b80d8

2011-02-10 05:09:34 +00:00

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