Matt Arsenault 798a829eca R600/SI: Match rsq instructions ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210226 91177308-0d34-0410-b5e6-96231b3b80d8		2014-06-05 00:15:55 +00:00
..
InstPrinter
MCTargetDesc
TargetInfo
AMDGPU.h	R600: Add definition for flat address space ID.	2014-05-22 18:27:07 +00:00
AMDGPU.td	R600/SI: Add a PredicateControl class for managing TableGen predicates	2014-05-16 20:56:45 +00:00
AMDGPUAsmPrinter.cpp
AMDGPUAsmPrinter.h
AMDGPUCallingConv.td
AMDGPUConvertToISA.cpp
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp	R600/SI: Refactor the VOP3_32 tablegen class	2014-05-16 20:56:47 +00:00
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td	R600: Add intrinsics for mad24	2014-05-22 18:00:15 +00:00
AMDGPUInstructions.td	R600/SI: Fix [s|u]int_to_fp for i1	2014-05-31 06:47:42 +00:00
AMDGPUIntrinsics.td	R600: Add intrinsics for mad24	2014-05-22 18:00:15 +00:00
AMDGPUISelDAGToDAG.cpp
AMDGPUISelLowering.cpp	R600: Set all float vector expands in the same place	2014-06-01 07:38:21 +00:00
AMDGPUISelLowering.h	R600: Implement ComputeNumSignBitsForTargetNode for BFE	2014-05-22 18:09:03 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp	Resolving MSVC warnings about switch statements with a default label, but no case labels. No functional changes intended.	2014-05-19 14:29:04 +00:00
AMDGPUMCInstLower.h	R600/SI: Refactor the VOP3_32 tablegen class	2014-05-16 20:56:47 +00:00
AMDGPURegisterInfo.cpp	Use range for	2014-05-15 21:44:05 +00:00
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp
AMDGPUSubtarget.h
AMDGPUTargetMachine.cpp	R600: Add definition for flat address space ID.	2014-05-22 18:27:07 +00:00
AMDGPUTargetMachine.h
AMDGPUTargetTransformInfo.cpp
AMDILBase.td
AMDILCFGStructurizer.cpp
AMDILInstrInfo.td
AMDILIntrinsicInfo.cpp
AMDILIntrinsicInfo.h
AMDILIntrinsics.td
AMDILISelLowering.cpp	Use range for	2014-05-15 21:44:05 +00:00
AMDILRegisterInfo.td
CaymanInstructions.td	R600: Expand mul24 for GPUs without it	2014-05-22 18:00:24 +00:00
CMakeLists.txt
EvergreenInstructions.td	R600: Expand mul24 for GPUs without it	2014-05-22 18:00:24 +00:00
LLVMBuild.txt
Makefile
Processors.td
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td	R600: Expand mul24 for GPUs without it	2014-05-22 18:00:24 +00:00
R600Intrinsics.td
R600ISelLowering.cpp	R600: Add dag combine for BFE	2014-05-22 18:09:07 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td
SIAnnotateControlFlow.cpp
SIDefines.h
SIFixSGPRCopies.cpp
SIInsertWaits.cpp
SIInstrFormats.td	R600/SI: Add a PredicateControl class for managing TableGen predicates	2014-05-16 20:56:45 +00:00
SIInstrInfo.cpp	Fix typos	2014-06-03 23:06:13 +00:00
SIInstrInfo.h	R600/SI: Refactor the VOP3_32 tablegen class	2014-05-16 20:56:47 +00:00
SIInstrInfo.td	R600/SI: Refactor the VOP3_32 tablegen class	2014-05-16 20:56:47 +00:00
SIInstructions.td	R600/SI: Match rsq instructions	2014-06-05 00:15:55 +00:00
SIIntrinsics.td
SIISelLowering.cpp	Use nullptr	2014-06-05 00:01:12 +00:00
SIISelLowering.h
SILowerControlFlow.cpp
SILowerI1Copies.cpp
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIRegisterInfo.cpp
SIRegisterInfo.h
SIRegisterInfo.td
SISchedule.td
SITypeRewriter.cpp