llvm-6502/test/CodeGen
2009-01-16 20:57:18 +00:00
..
Alpha Fix Alpha test and support for private linkage. 2009-01-15 21:51:46 +00:00
ARM Add the private linkage. 2009-01-15 20:18:42 +00:00
CBackend
CellSPU Add the private linkage. 2009-01-15 20:18:42 +00:00
CPP
Generic The list-td and list-tdrr schedulers don't yet support physreg 2009-01-13 20:24:13 +00:00
IA64 Add the private linkage. 2009-01-15 20:18:42 +00:00
Mips Add the private linkage. 2009-01-15 20:18:42 +00:00
PowerPC Add the private linkage. 2009-01-15 20:18:42 +00:00
SPARC Add the private linkage. 2009-01-15 20:18:42 +00:00
X86 CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions. 2009-01-16 20:57:18 +00:00
XCore Add the private linkage. 2009-01-15 20:18:42 +00:00