Evan Cheng 8239daf7c8 Two sets of changes. Sorry they are intermingled. ... 1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8		2010-11-03 00:45:17 +00:00
..
Analysis	Teach memdep to use pointsToConstantMemory to determine that loads	2010-10-29 01:14:04 +00:00
Archive
Assembler
Bindings/Ocaml
Bitcode	Testcase for PR8494 (invalid bitcode crashing the bitcode reader).	2010-10-28 15:57:30 +00:00
BugPoint
CodeGen	Two sets of changes. Sorry they are intermingled.	2010-11-03 00:45:17 +00:00
DebugInfo
ExecutionEngine	The ARM jit cannot handle these tests as of 2010-10-27.	2010-10-29 00:23:43 +00:00
Feature
FrontendAda
FrontendC
FrontendC++
FrontendFortran
FrontendObjC
FrontendObjC++
Integer
lib
Linker
LLVMC
MC	chase owen.	2010-11-02 23:55:24 +00:00
Other
Scripts	test/Scripts/macho-dump: Make hack for Python-2.4. [PR7995]	2010-10-29 01:14:16 +00:00
TableGen
Transforms	When folding away a (shl (shr)) pair, we need to check that the bits that will BECOME the low	2010-11-01 21:08:20 +00:00
Unit
Verifier
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
site.exp.in
TestRunner.sh