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llvm-6502/test/CodeGen
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Evan Cheng 8239daf7c8 Two sets of changes. Sorry they are intermingled. 
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
   "optimize for latency". Call instructions don't have the right latency and
   this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
   not # of micro-ops since multi-latency instructions is completely executed
   even when the predicate is false. Also, some instruction will be "slower"
   when they are predicated due to the register def becoming implicit input.
   rdar://8598427


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 00:45:17 +00:00
..
Alpha
ARM Two sets of changes. Sorry they are intermingled. 2010-11-03 00:45:17 +00:00
Blackfin
CBackend
CellSPU Change v64 datalayout in SPU. 2010-10-26 10:45:47 +00:00
CPP
Generic
MBlaze Recommit 116986 with capitalization typo fixed. 2010-10-21 03:57:26 +00:00
Mips
MSP430 Inline asm mult-alt constraint tests. 2010-11-02 23:01:44 +00:00
PowerPC Inline asm mult-alt constraint tests. 2010-11-02 23:01:44 +00:00
PTX Add test case mov.ll for PTX device function 2010-10-19 13:21:51 +00:00
SPARC Inline asm mult-alt constraint tests. 2010-11-02 23:01:44 +00:00
SystemZ
Thumb Overhaul memory barriers in the ARM backend. Radar 8601999. 2010-10-30 00:54:37 +00:00
Thumb2 Two sets of changes. Sorry they are intermingled. 2010-11-03 00:45:17 +00:00
X86 Inline asm mult-alt constraint tests. 2010-11-02 23:01:44 +00:00
XCore
thumb2-mul.ll