Bill Wendling e6b293b78d Forgot the part where we handle the ".llvm.eh.catch.all.value". ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99697 91177308-0d34-0410-b5e6-96231b3b80d8		2010-03-27 01:24:30 +00:00
..
CallingConvLower.cpp
CMakeLists.txt
DAGCombiner.cpp	fix PR6533 by updating the br(xor) code to remember the case	2010-03-10 23:46:44 +00:00
FastISel.cpp	Remove dead include.	2010-03-11 02:28:48 +00:00
FunctionLoweringInfo.cpp	Forgot the part where we handle the ".llvm.eh.catch.all.value".	2010-03-27 01:24:30 +00:00
FunctionLoweringInfo.h
InstrEmitter.cpp	LiveVariables should clear kill / dead markers first. This allows us to remove a hack in the scheduler.	2010-03-26 02:12:24 +00:00
InstrEmitter.h	reapply 99444/99445, which I speculatively reverted in	2010-03-25 04:41:16 +00:00
LegalizeDAG.cpp	Get rid of target-specific nodes for fp16 <-> fp32 conversion.	2010-03-18 22:35:37 +00:00
LegalizeFloatTypes.cpp	Turn calls to copysignl into an FCOPYSIGN node. Handle FCOPYSIGN nodes	2010-03-14 21:08:40 +00:00
LegalizeIntegerTypes.cpp	Revert 99335. getTypeToExpandTo's iterative behavior is actually	2010-03-23 22:44:42 +00:00
LegalizeTypes.cpp	Remove dead parameter passing.	2010-03-02 01:55:18 +00:00
LegalizeTypes.h	Turn calls to copysignl into an FCOPYSIGN node. Handle FCOPYSIGN nodes	2010-03-14 21:08:40 +00:00
LegalizeTypesGeneric.cpp	Add non-temporal flags and remove an assumption of default arguments.	2010-02-15 17:00:31 +00:00
LegalizeVectorOps.cpp
LegalizeVectorTypes.cpp	Fixed a widening bug where we were not using the correct size for the load	2010-03-19 01:19:52 +00:00
Makefile
ScheduleDAGFast.cpp
ScheduleDAGList.cpp
ScheduleDAGRRList.cpp
ScheduleDAGSDNodes.cpp	Scheduler assumes SDDbgValue nodes are in source order. That's true currently. But add an assertion to verify it.	2010-03-25 07:16:57 +00:00
ScheduleDAGSDNodes.h
SDNodeDbgValue.h	Make sure SDDbgValue.Invalid is initialized to false by all the constructors.	2010-03-25 05:50:26 +00:00
SDNodeOrdering.h
SelectionDAG.cpp	Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers.	2010-03-25 01:38:16 +00:00
SelectionDAGBuilder.cpp	Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers.	2010-03-25 01:38:16 +00:00
SelectionDAGBuilder.h
SelectionDAGISel.cpp	Change tblgen to emit FOOISD opcode names as two	2010-03-25 06:33:05 +00:00
SelectionDAGPrinter.cpp
TargetLowering.cpp	Add few missed libcalls and correct names for others.	2010-03-26 21:32:14 +00:00