Tom Stellard e7ac2ed1c2 R600: Add IsExport bit to TableGen instruction definitions ... Tested-by: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188516 91177308-0d34-0410-b5e6-96231b3b80d8		2013-08-16 01:11:51 +00:00
..
Analysis	Fix an oversight in isPotentiallyReachable where we wouldn't do any CFG-walking	2013-08-13 00:03:47 +00:00
AsmParser
Bitcode
CodeGen	Make a few more things const.	2013-08-15 20:25:44 +00:00
DebugInfo	Store compile unit corresponding to each chain of inlined debug info entries. No functionality change.	2013-08-06 10:49:15 +00:00
ExecutionEngine	Support X86_64_GOTLoad relocations in RuntimeDyldMachO by treating them the	2013-08-15 22:31:40 +00:00
IR	[Mips][msa] Value types for MSA support.	2013-08-13 22:34:26 +00:00
IRReader
Linker
MC	Support C99 hexadecimal floating-point literals in assembly	2013-08-14 14:23:31 +00:00
Object	Add back missing PPC relocation types.	2013-08-09 09:42:14 +00:00
Option	Options: explicit handling of --	2013-08-13 22:23:05 +00:00
Support	Tighten up the yamilizer so it stops eliding empty sequences if the embedded empty sequence is the first key/value in a map which is itself in a sequence.	2013-08-15 23:17:53 +00:00
TableGen	Remove some std stream usage from Support and TableGen	2013-08-06 22:51:21 +00:00
Target	R600: Add IsExport bit to TableGen instruction definitions	2013-08-16 01:11:51 +00:00
Transforms	InstCombine: Simplify if(x!=0 && x!=-1).	2013-08-16 00:15:20 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile