Benjamin Kramer f50125ecaa DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is illegal. The latter usually compiles into smaller code. ... example code: unsigned foo(unsigned x, unsigned y) { if (x != 0) y--; return y; } before: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] sbbl %eax, %eax ## encoding: [0x19,0xc0] notl %eax ## encoding: [0xf7,0xd0] addl 8(%esp), %eax ## encoding: [0x03,0x44,0x24,0x08] ret ## encoding: [0xc3] after: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] movl 8(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08] adcl $-1, %eax ## encoding: [0x83,0xd0,0xff] ret ## encoding: [0xc3] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122455 91177308-0d34-0410-b5e6-96231b3b80d8		2010-12-22 23:17:45 +00:00
..
Alpha
ARM	Add ARM-specific DAG combining to cast i64 vector element load/stores to f64.	2010-12-21 06:43:19 +00:00
Blackfin
CBackend
CellSPU	Don't feed 19 bit immediates to ILA.	2010-12-17 09:36:09 +00:00
CPP
Generic	temporarily disable this: PR8823.	2010-12-20 02:11:23 +00:00
MBlaze	Lower the MBlaze target specific calling conventions for "interrupt_handler"	2010-12-15 20:27:28 +00:00
Mips	Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka	2010-12-09 17:32:30 +00:00
MSP430
PowerPC	Restore the behavior of frame lowering before my refactoring.	2010-12-18 19:53:14 +00:00
PTX	ptx: add ld instruction and test	2010-12-22 10:38:51 +00:00
SPARC
SystemZ
Thumb	Thumb1 had two patterns for the same load-from-constant-pool instruction.	2010-12-15 23:52:36 +00:00
Thumb2	Remove the rest of the *_sfp Neon instruction patterns.	2010-12-13 23:02:37 +00:00
X86	DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is illegal. The latter usually compiles into smaller code.	2010-12-22 23:17:45 +00:00
XCore
thumb2-mul.ll