llvm-6502/test/CodeGen
James Y Knight e9359f427e Fix alignment checks in MergeConsecutiveStores.
1) check whether the alignment of the memory is sufficient for the
*merged* store or load to be efficient.

Not doing so can result in some ridiculously poor code generation, if
merging creates a vector operation which must be aligned but isn't.

2) DON'T check that the alignment of each load/store is equal. If
you're merging 2 4-byte stores, the first *might* have 8-byte
alignment, but the second certainly will have 4-byte alignment. We do
want to allow those to be merged.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236850 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-08 13:47:01 +00:00
..
AArch64 [AArch64] Fix sext/zext folding in address arithmetic. 2015-05-07 19:21:36 +00:00
ARM Clear kill flags in tail duplication. 2015-05-07 21:48:26 +00:00
BPF [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
CPP [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
Generic [Hexagon] r236351 fix does not work on builder configurations yet. 2015-05-01 22:39:20 +00:00
Hexagon IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
Inputs IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
Mips [mips] Emit the .insn directive for empty basic blocks. 2015-05-08 09:10:15 +00:00
MSP430 [opaque pointer type] Add textual IR support for explicit type parameter to gep operator 2015-03-13 18:20:45 +00:00
NVPTX [NVPTX] Handle addrspacecast constant expressions in aggregate initializers 2015-04-28 17:18:30 +00:00
PowerPC Fix alignment checks in MergeConsecutiveStores. 2015-05-08 13:47:01 +00:00
R600 R600/SI: Add VCC as an implict def of SI_KILL 2015-05-01 03:44:09 +00:00
SPARC [opaque pointer type] Add textual IR support for explicit type parameter to the call instruction 2015-04-16 23:24:18 +00:00
SystemZ [DAGCombiner] Account for getVectorIdxTy() when narrowing vector load 2015-05-05 19:34:10 +00:00
Thumb IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
Thumb2 Thumb2SizeReduction: Check the correct set of registers for LDMIA. 2015-05-05 20:07:10 +00:00
WinEH Flip r236172 testcase RUN option ordering for BSD sed(1). NFC. 2015-04-30 00:07:34 +00:00
X86 Fix alignment checks in MergeConsecutiveStores. 2015-05-08 13:47:01 +00:00
XCore IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00