Tim Northover e93c701cac ARM: fix VEXT encoding corner case ... The disassembly of VEXT instructions was too lax in the bits checked. This fixes the case where the instruction affects Q-registers but a misaligned lane was specified (should be UNDEFINED). Patch by Amaury de la Vieuville git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-31 13:47:25 +00:00
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AArch64	AArch64: implement ETMv4 trace system registers.	2013-04-03 12:31:29 +00:00
ARM	ARM: fix VEXT encoding corner case	2013-05-31 13:47:25 +00:00
MBlaze	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
Mips	[mips] DSP-ASE move from HI/LO register instructions.	2013-04-18 00:52:44 +00:00
SystemZ	[SystemZ] Immediate compare-and-branch support	2013-05-29 11:58:52 +00:00
X86	Add CLAC/STAC instruction encoding/decoding support	2013-04-11 04:52:28 +00:00
XCore	[XCore] Add LDAPB instructions.	2013-05-05 13:36:53 +00:00