llvm-6502/test/CodeGen/ARM/neon_cmp.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

17 lines
540 B
LLVM

; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s
; bug 15283
; radar://13191881
; CHECK: vfcmp
define void @vfcmp(<2 x double>* %a, <2 x double>* %b) {
%wide.load = load <2 x double>, <2 x double>* %a, align 4
%wide.load2 = load <2 x double>, <2 x double>* %b, align 4
; CHECK-NOT: vdup.32
; CHECK-NOT: vmovn.i64
%v1 = fcmp olt <2 x double> %wide.load, %wide.load2
%v2 = zext <2 x i1> %v1 to <2 x i32>
%v3 = sitofp <2 x i32> %v2 to <2 x double>
store <2 x double> %v3, <2 x double>* %b, align 4
ret void
}