mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
ba61446a56
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206877 91177308-0d34-0410-b5e6-96231b3b80d8
135 lines
4.3 KiB
LLVM
135 lines
4.3 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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; arm64 has a different approach to scalars. Discarding.
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define float @test_vcvts_f32_s32(i32 %a) {
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; CHECK: test_vcvts_f32_s32
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; CHECK: scvtf {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%vcvtf.i = insertelement <1 x i32> undef, i32 %a, i32 0
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%0 = call float @llvm.aarch64.neon.vcvtint2fps.f32.v1i32(<1 x i32> %vcvtf.i)
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ret float %0
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}
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declare float @llvm.aarch64.neon.vcvtint2fps.f32.v1i32(<1 x i32>)
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define double @test_vcvtd_f64_s64(i64 %a) {
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; CHECK: test_vcvtd_f64_s64
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; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}
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entry:
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%vcvtf.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%0 = call double @llvm.aarch64.neon.vcvtint2fps.f64.v1i64(<1 x i64> %vcvtf.i)
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ret double %0
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}
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declare double @llvm.aarch64.neon.vcvtint2fps.f64.v1i64(<1 x i64>)
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define float @test_vcvts_f32_u32(i32 %a) {
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; CHECK: test_vcvts_f32_u32
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; CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%vcvtf.i = insertelement <1 x i32> undef, i32 %a, i32 0
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%0 = call float @llvm.aarch64.neon.vcvtint2fpu.f32.v1i32(<1 x i32> %vcvtf.i)
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ret float %0
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}
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declare float @llvm.aarch64.neon.vcvtint2fpu.f32.v1i32(<1 x i32>)
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define double @test_vcvtd_f64_u64(i64 %a) {
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; CHECK: test_vcvtd_f64_u64
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; CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}}
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entry:
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%vcvtf.i = insertelement <1 x i64> undef, i64 %a, i32 0
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%0 = call double @llvm.aarch64.neon.vcvtint2fpu.f64.v1i64(<1 x i64> %vcvtf.i)
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ret double %0
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}
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declare double @llvm.aarch64.neon.vcvtint2fpu.f64.v1i64(<1 x i64>)
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define float @test_vcvts_n_f32_s32(i32 %a) {
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; CHECK: test_vcvts_n_f32_s32
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; CHECK: scvtf {{s[0-9]+}}, {{s[0-9]+}}, #1
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entry:
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%vcvtf = insertelement <1 x i32> undef, i32 %a, i32 0
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%0 = call float @llvm.aarch64.neon.vcvtfxs2fp.n.f32.v1i32(<1 x i32> %vcvtf, i32 1)
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ret float %0
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}
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declare float @llvm.aarch64.neon.vcvtfxs2fp.n.f32.v1i32(<1 x i32>, i32)
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define double @test_vcvtd_n_f64_s64(i64 %a) {
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; CHECK: test_vcvtd_n_f64_s64
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; CHECK: scvtf {{d[0-9]+}}, {{d[0-9]+}}, #1
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entry:
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%vcvtf = insertelement <1 x i64> undef, i64 %a, i32 0
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%0 = call double @llvm.aarch64.neon.vcvtfxs2fp.n.f64.v1i64(<1 x i64> %vcvtf, i32 1)
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ret double %0
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}
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declare double @llvm.aarch64.neon.vcvtfxs2fp.n.f64.v1i64(<1 x i64>, i32)
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define float @test_vcvts_n_f32_u32(i32 %a) {
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; CHECK: test_vcvts_n_f32_u32
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; CHECK: ucvtf {{s[0-9]+}}, {{s[0-9]+}}, #1
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entry:
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%vcvtf = insertelement <1 x i32> undef, i32 %a, i32 0
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%0 = call float @llvm.aarch64.neon.vcvtfxu2fp.n.f32.v1i32(<1 x i32> %vcvtf, i32 1)
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ret float %0
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}
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declare float @llvm.aarch64.neon.vcvtfxu2fp.n.f32.v1i32(<1 x i32>, i32)
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define double @test_vcvtd_n_f64_u64(i64 %a) {
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; CHECK: test_vcvtd_n_f64_u64
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; CHECK: ucvtf {{d[0-9]+}}, {{d[0-9]+}}, #1
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entry:
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%vcvtf = insertelement <1 x i64> undef, i64 %a, i32 0
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%0 = call double @llvm.aarch64.neon.vcvtfxu2fp.n.f64.v1i64(<1 x i64> %vcvtf, i32 1)
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ret double %0
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}
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declare double @llvm.aarch64.neon.vcvtfxu2fp.n.f64.v1i64(<1 x i64>, i32)
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define i32 @test_vcvts_n_s32_f32(float %a) {
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; CHECK: test_vcvts_n_s32_f32
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; CHECK: fcvtzs {{s[0-9]+}}, {{s[0-9]+}}, #1
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entry:
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%fcvtzs1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.f32(float %a, i32 1)
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%0 = extractelement <1 x i32> %fcvtzs1, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i32.f32(float, i32)
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define i64 @test_vcvtd_n_s64_f64(double %a) {
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; CHECK: test_vcvtd_n_s64_f64
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; CHECK: fcvtzs {{d[0-9]+}}, {{d[0-9]+}}, #1
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entry:
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%fcvtzs1 = call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.f64(double %a, i32 1)
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%0 = extractelement <1 x i64> %fcvtzs1, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxs.n.v1i64.f64(double, i32)
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define i32 @test_vcvts_n_u32_f32(float %a) {
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; CHECK: test_vcvts_n_u32_f32
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; CHECK: fcvtzu {{s[0-9]+}}, {{s[0-9]+}}, #32
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entry:
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%fcvtzu1 = call <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.f32(float %a, i32 32)
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%0 = extractelement <1 x i32> %fcvtzu1, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i32.f32(float, i32)
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define i64 @test_vcvtd_n_u64_f64(double %a) {
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; CHECK: test_vcvtd_n_u64_f64
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; CHECK: fcvtzu {{d[0-9]+}}, {{d[0-9]+}}, #64
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entry:
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%fcvtzu1 = tail call <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.f64(double %a, i32 64)
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%0 = extractelement <1 x i64> %fcvtzu1, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.vcvtfp2fxu.n.v1i64.f64(double, i32)
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