mirror of
https://github.com/c64scene-ar/llvm-6502.git
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c499ecd1d1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206887 91177308-0d34-0410-b5e6-96231b3b80d8
235 lines
6.5 KiB
LLVM
235 lines
6.5 KiB
LLVM
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
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; arm64 duplicates these tests in cvt.ll
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;; Scalar Floating-point Convert
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define float @test_vcvtxn(double %a) {
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; CHECK: test_vcvtxn
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; CHECK: fcvtxn {{s[0-9]}}, {{d[0-9]}}
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entry:
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%vcvtf = call float @llvm.aarch64.neon.fcvtxn(double %a)
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ret float %vcvtf
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}
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declare float @llvm.aarch64.neon.fcvtxn(double)
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define i32 @test_vcvtass(float %a) {
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; CHECK: test_vcvtass
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; CHECK: fcvtas {{s[0-9]}}, {{s[0-9]}}
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entry:
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%vcvtas1.i = call <1 x i32> @llvm.aarch64.neon.fcvtas.v1i32.f32(float %a)
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%0 = extractelement <1 x i32> %vcvtas1.i, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.fcvtas.v1i32.f32(float)
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define i64 @test_test_vcvtasd(double %a) {
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; CHECK: test_test_vcvtasd
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; CHECK: fcvtas {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcvtas1.i = call <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.f64(double %a)
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%0 = extractelement <1 x i64> %vcvtas1.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.f64(double)
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define i32 @test_vcvtaus(float %a) {
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; CHECK: test_vcvtaus
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; CHECK: fcvtau {{s[0-9]}}, {{s[0-9]}}
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entry:
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%vcvtau1.i = call <1 x i32> @llvm.aarch64.neon.fcvtau.v1i32.f32(float %a)
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%0 = extractelement <1 x i32> %vcvtau1.i, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.fcvtau.v1i32.f32(float)
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define i64 @test_vcvtaud(double %a) {
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; CHECK: test_vcvtaud
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; CHECK: fcvtau {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcvtau1.i = call <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.f64(double %a)
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%0 = extractelement <1 x i64> %vcvtau1.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.f64(double)
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define i32 @test_vcvtmss(float %a) {
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; CHECK: test_vcvtmss
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; CHECK: fcvtms {{s[0-9]}}, {{s[0-9]}}
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entry:
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%vcvtms1.i = call <1 x i32> @llvm.aarch64.neon.fcvtms.v1i32.f32(float %a)
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%0 = extractelement <1 x i32> %vcvtms1.i, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.fcvtms.v1i32.f32(float)
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define i64 @test_vcvtmd_s64_f64(double %a) {
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; CHECK: test_vcvtmd_s64_f64
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; CHECK: fcvtms {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcvtms1.i = call <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.f64(double %a)
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%0 = extractelement <1 x i64> %vcvtms1.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.f64(double)
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define i32 @test_vcvtmus(float %a) {
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; CHECK: test_vcvtmus
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; CHECK: fcvtmu {{s[0-9]}}, {{s[0-9]}}
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entry:
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%vcvtmu1.i = call <1 x i32> @llvm.aarch64.neon.fcvtmu.v1i32.f32(float %a)
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%0 = extractelement <1 x i32> %vcvtmu1.i, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.fcvtmu.v1i32.f32(float)
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define i64 @test_vcvtmud(double %a) {
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; CHECK: test_vcvtmud
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; CHECK: fcvtmu {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcvtmu1.i = call <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.f64(double %a)
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%0 = extractelement <1 x i64> %vcvtmu1.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.f64(double)
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define i32 @test_vcvtnss(float %a) {
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; CHECK: test_vcvtnss
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; CHECK: fcvtns {{s[0-9]}}, {{s[0-9]}}
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entry:
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%vcvtns1.i = call <1 x i32> @llvm.aarch64.neon.fcvtns.v1i32.f32(float %a)
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%0 = extractelement <1 x i32> %vcvtns1.i, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.fcvtns.v1i32.f32(float)
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define i64 @test_vcvtnd_s64_f64(double %a) {
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; CHECK: test_vcvtnd_s64_f64
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; CHECK: fcvtns {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcvtns1.i = call <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.f64(double %a)
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%0 = extractelement <1 x i64> %vcvtns1.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.f64(double)
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define i32 @test_vcvtnus(float %a) {
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; CHECK: test_vcvtnus
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; CHECK: fcvtnu {{s[0-9]}}, {{s[0-9]}}
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entry:
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%vcvtnu1.i = call <1 x i32> @llvm.aarch64.neon.fcvtnu.v1i32.f32(float %a)
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%0 = extractelement <1 x i32> %vcvtnu1.i, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.fcvtnu.v1i32.f32(float)
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define i64 @test_vcvtnud(double %a) {
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; CHECK: test_vcvtnud
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; CHECK: fcvtnu {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcvtnu1.i = call <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.f64(double %a)
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%0 = extractelement <1 x i64> %vcvtnu1.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.f64(double)
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define i32 @test_vcvtpss(float %a) {
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; CHECK: test_vcvtpss
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; CHECK: fcvtps {{s[0-9]}}, {{s[0-9]}}
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entry:
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%vcvtps1.i = call <1 x i32> @llvm.aarch64.neon.fcvtps.v1i32.f32(float %a)
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%0 = extractelement <1 x i32> %vcvtps1.i, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.fcvtps.v1i32.f32(float)
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define i64 @test_vcvtpd_s64_f64(double %a) {
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; CHECK: test_vcvtpd_s64_f64
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; CHECK: fcvtps {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcvtps1.i = call <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.f64(double %a)
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%0 = extractelement <1 x i64> %vcvtps1.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.f64(double)
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define i32 @test_vcvtpus(float %a) {
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; CHECK: test_vcvtpus
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; CHECK: fcvtpu {{s[0-9]}}, {{s[0-9]}}
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entry:
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%vcvtpu1.i = call <1 x i32> @llvm.aarch64.neon.fcvtpu.v1i32.f32(float %a)
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%0 = extractelement <1 x i32> %vcvtpu1.i, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.fcvtpu.v1i32.f32(float)
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define i64 @test_vcvtpud(double %a) {
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; CHECK: test_vcvtpud
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; CHECK: fcvtpu {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcvtpu1.i = call <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.f64(double %a)
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%0 = extractelement <1 x i64> %vcvtpu1.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.f64(double)
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define i32 @test_vcvtss(float %a) {
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; CHECK: test_vcvtss
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; CHECK: fcvtzs {{s[0-9]}}, {{s[0-9]}}
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entry:
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%vcvtzs1.i = call <1 x i32> @llvm.aarch64.neon.fcvtzs.v1i32.f32(float %a)
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%0 = extractelement <1 x i32> %vcvtzs1.i, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.fcvtzs.v1i32.f32(float)
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define i64 @test_vcvtd_s64_f64(double %a) {
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; CHECK: test_vcvtd_s64_f64
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; CHECK: fcvtzs {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcvzs1.i = call <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.f64(double %a)
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%0 = extractelement <1 x i64> %vcvzs1.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.f64(double)
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define i32 @test_vcvtus(float %a) {
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; CHECK: test_vcvtus
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; CHECK: fcvtzu {{s[0-9]}}, {{s[0-9]}}
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entry:
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%vcvtzu1.i = call <1 x i32> @llvm.aarch64.neon.fcvtzu.v1i32.f32(float %a)
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%0 = extractelement <1 x i32> %vcvtzu1.i, i32 0
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ret i32 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.fcvtzu.v1i32.f32(float)
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define i64 @test_vcvtud(double %a) {
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; CHECK: test_vcvtud
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; CHECK: fcvtzu {{d[0-9]}}, {{d[0-9]}}
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entry:
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%vcvtzu1.i = call <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.f64(double %a)
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%0 = extractelement <1 x i64> %vcvtzu1.i, i32 0
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ret i64 %0
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}
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declare <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.f64(double)
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