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https://github.com/c64scene-ar/llvm-6502.git
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c499ecd1d1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206887 91177308-0d34-0410-b5e6-96231b3b80d8
177 lines
7.4 KiB
LLVM
177 lines
7.4 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast
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; arm64 has separate copy as aarch64-neon-vector-list-spill.ll
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; FIXME: We should not generate ld/st for such register spill/fill, because the
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; test case seems very simple and the register pressure is not high. If the
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; spill/fill algorithm is optimized, this test case may not be triggered. And
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; then we can delete it.
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define i32 @spill.DPairReg(i8* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.DPairReg:
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; CHECK: ld2 {v{{[0-9]+}}.2s, v{{[0-9]+}}.2s}, [{{x[0-9]+|sp}}]
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; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2.v2i32(i8* %arg1, i32 4)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <2 x i32>, <2 x i32> } %vld, 0
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%res = extractelement <2 x i32> %vld.extract, i32 1
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ret i32 %res
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}
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define i16 @spill.DTripleReg(i8* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.DTripleReg:
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; CHECK: ld3 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [{{x[0-9]+|sp}}]
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; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3.v4i16(i8* %arg1, i32 4)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <4 x i16>, <4 x i16>, <4 x i16> } %vld, 0
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%res = extractelement <4 x i16> %vld.extract, i32 1
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ret i16 %res
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}
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define i16 @spill.DQuadReg(i8* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.DQuadReg:
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; CHECK: ld4 {v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h}, [{{x[0-9]+|sp}}]
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; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4.v4i16(i8* %arg1, i32 4)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %vld, 0
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%res = extractelement <4 x i16> %vld.extract, i32 0
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ret i16 %res
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}
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define i32 @spill.QPairReg(i8* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.QPairReg:
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; CHECK: ld3 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}]
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; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32(i8* %arg1, i32 4)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <4 x i32>, <4 x i32> } %vld, 0
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%res = extractelement <4 x i32> %vld.extract, i32 1
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ret i32 %res
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}
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define float @spill.QTripleReg(i8* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.QTripleReg:
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; CHECK: ld3 {v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s}, [{{x[0-9]+|sp}}]
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; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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entry:
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%vld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld3.v4f32(i8* %arg1, i32 4)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld3.extract = extractvalue { <4 x float>, <4 x float>, <4 x float> } %vld3, 0
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%res = extractelement <4 x float> %vld3.extract, i32 1
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ret float %res
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}
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define i8 @spill.QQuadReg(i8* %arg1, i32 %arg2) {
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; CHECK-LABEL: spill.QQuadReg:
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; CHECK: ld4 {v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d}, [{{x[0-9]+|sp}}]
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; CHECK: st1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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; CHECK: ld1 {v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b}, [{{x[0-9]+|sp}}]
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entry:
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%vld = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4.v16i8(i8* %arg1, i32 4)
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%cmp = icmp eq i32 %arg2, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo()
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br label %if.end
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if.end:
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%vld.extract = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vld, 0
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%res = extractelement <16 x i8> %vld.extract, i32 1
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ret i8 %res
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}
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declare { <2 x i32>, <2 x i32> } @llvm.arm.neon.vld2.v2i32(i8*, i32)
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declare { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld3.v4i16(i8*, i32)
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declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.arm.neon.vld4.v4i16(i8*, i32)
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declare { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32(i8*, i32)
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declare { <4 x float>, <4 x float>, <4 x float> } @llvm.arm.neon.vld3.v4f32(i8*, i32)
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declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld4.v16i8(i8*, i32)
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declare void @foo()
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; FIXME: We should not generate ld/st for such register spill/fill, because the
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; test case seems very simple and the register pressure is not high. If the
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; spill/fill algorithm is optimized, this test case may not be triggered. And
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; then we can delete it.
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; check the spill for Register Class QPair_with_qsub_0_in_FPR128Lo
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define <8 x i16> @test_2xFPR128Lo(i64 %got, i8* %ptr, <1 x i64> %a) {
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tail call void @llvm.arm.neon.vst2lane.v1i64(i8* %ptr, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, i32 0, i32 8)
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tail call void @foo()
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%sv = shufflevector <1 x i64> zeroinitializer, <1 x i64> %a, <2 x i32> <i32 0, i32 1>
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%1 = bitcast <2 x i64> %sv to <8 x i16>
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%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
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%3 = mul <8 x i16> %2, %2
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ret <8 x i16> %3
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}
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; check the spill for Register Class QTriple_with_qsub_0_in_FPR128Lo
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define <8 x i16> @test_3xFPR128Lo(i64 %got, i8* %ptr, <1 x i64> %a) {
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tail call void @llvm.arm.neon.vst3lane.v1i64(i8* %ptr, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, i32 0, i32 8)
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tail call void @foo()
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%sv = shufflevector <1 x i64> zeroinitializer, <1 x i64> %a, <2 x i32> <i32 0, i32 1>
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%1 = bitcast <2 x i64> %sv to <8 x i16>
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%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
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%3 = mul <8 x i16> %2, %2
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ret <8 x i16> %3
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}
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; check the spill for Register Class QQuad_with_qsub_0_in_FPR128Lo
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define <8 x i16> @test_4xFPR128Lo(i64 %got, i8* %ptr, <1 x i64> %a) {
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tail call void @llvm.arm.neon.vst4lane.v1i64(i8* %ptr, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, <1 x i64> zeroinitializer, i32 0, i32 8)
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tail call void @foo()
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%sv = shufflevector <1 x i64> zeroinitializer, <1 x i64> %a, <2 x i32> <i32 0, i32 1>
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%1 = bitcast <2 x i64> %sv to <8 x i16>
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%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
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%3 = mul <8 x i16> %2, %2
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ret <8 x i16> %3
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}
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declare void @llvm.arm.neon.vst2lane.v1i64(i8*, <1 x i64>, <1 x i64>, i32, i32)
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declare void @llvm.arm.neon.vst3lane.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, i32, i32)
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declare void @llvm.arm.neon.vst4lane.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32, i32)
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