mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
fe6f4e4d31
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207101 91177308-0d34-0410-b5e6-96231b3b80d8
203 lines
7.8 KiB
LLVM
203 lines
7.8 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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; arm64: This test contains much that is unique and valuable. Unfortunately the
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; bits that are unique aren't valuable and the bits that are valuable aren't
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; unique. (weird ABI types vs bog-standard shifting & extensions).
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; For formal arguments, we have the following vector type promotion,
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; v2i8 is promoted to v2i32(f64)
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; v2i16 is promoted to v2i32(f64)
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; v4i8 is promoted to v4i16(f64)
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; v8i1 is promoted to v8i16(f128)
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define <2 x i8> @test_sext_inreg_v2i8i16(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i8i16
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; CHECK: sshll v0.8h, v0.8b, #0
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
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; CHECK-NEXT: sshll v1.8h, v1.8b, #0
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; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
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%1 = sext <2 x i8> %v1 to <2 x i16>
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%2 = sext <2 x i8> %v2 to <2 x i16>
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%3 = shufflevector <2 x i16> %1, <2 x i16> %2, <2 x i32> <i32 0, i32 2>
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%4 = trunc <2 x i16> %3 to <2 x i8>
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ret <2 x i8> %4
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}
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define <2 x i8> @test_sext_inreg_v2i8i16_2(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i8i16_2
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; CHECK: sshll v0.8h, v0.8b, #0
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
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; CHECK-NEXT: sshll v1.8h, v1.8b, #0
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; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
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%a1 = shl <2 x i32> %v1, <i32 24, i32 24>
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%a2 = ashr <2 x i32> %a1, <i32 24, i32 24>
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%b1 = shl <2 x i32> %v2, <i32 24, i32 24>
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%b2 = ashr <2 x i32> %b1, <i32 24, i32 24>
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%c = shufflevector <2 x i32> %a2, <2 x i32> %b2, <2 x i32> <i32 0, i32 2>
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%d = trunc <2 x i32> %c to <2 x i8>
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ret <2 x i8> %d
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}
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define <2 x i8> @test_sext_inreg_v2i8i32(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i8i32
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; CHECK: sshll v0.8h, v0.8b, #0
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
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; CHECK-NEXT: sshll v1.8h, v1.8b, #0
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; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
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%1 = sext <2 x i8> %v1 to <2 x i32>
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%2 = sext <2 x i8> %v2 to <2 x i32>
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%3 = shufflevector <2 x i32> %1, <2 x i32> %2, <2 x i32> <i32 0, i32 2>
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%4 = trunc <2 x i32> %3 to <2 x i8>
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ret <2 x i8> %4
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}
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define <2 x i8> @test_sext_inreg_v2i8i64(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i8i64
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; CHECK: ushll v1.2d, v1.2s, #0
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; CHECK: ushll v0.2d, v0.2s, #0
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; CHECK: shl v0.2d, v0.2d, #56
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; CHECK: sshr v0.2d, v0.2d, #56
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; CHECK: shl v1.2d, v1.2d, #56
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; CHECK: sshr v1.2d, v1.2d, #56
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%1 = sext <2 x i8> %v1 to <2 x i64>
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%2 = sext <2 x i8> %v2 to <2 x i64>
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%3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 2>
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%4 = trunc <2 x i64> %3 to <2 x i8>
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ret <2 x i8> %4
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}
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define <4 x i8> @test_sext_inreg_v4i8i16(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v4i8i16
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; CHECK: sshll v0.8h, v0.8b, #0
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
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; CHECK-NEXT: sshll v1.8h, v1.8b, #0
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; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
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%1 = sext <4 x i8> %v1 to <4 x i16>
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%2 = sext <4 x i8> %v2 to <4 x i16>
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%3 = shufflevector <4 x i16> %1, <4 x i16> %2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%4 = trunc <4 x i16> %3 to <4 x i8>
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ret <4 x i8> %4
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}
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define <4 x i8> @test_sext_inreg_v4i8i16_2(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v4i8i16_2
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; CHECK: sshll v0.8h, v0.8b, #0
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; CHECK-NEXT: uzp1 v0.8h, v0.8h, v0.8h
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; CHECK-NEXT: sshll v1.8h, v1.8b, #0
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; CHECK-NEXT: uzp1 v1.8h, v1.8h, v1.8h
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%a1 = shl <4 x i16> %v1, <i16 8, i16 8, i16 8, i16 8>
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%a2 = ashr <4 x i16> %a1, <i16 8, i16 8, i16 8, i16 8>
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%b1 = shl <4 x i16> %v2, <i16 8, i16 8, i16 8, i16 8>
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%b2 = ashr <4 x i16> %b1, <i16 8, i16 8, i16 8, i16 8>
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%c = shufflevector <4 x i16> %a2, <4 x i16> %b2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%d = trunc <4 x i16> %c to <4 x i8>
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ret <4 x i8> %d
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}
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define <4 x i8> @test_sext_inreg_v4i8i32(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v4i8i32
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; CHECK: ushll v1.4s, v1.4h, #0
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; CHECK: ushll v0.4s, v0.4h, #0
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; CHECK: shl v0.4s, v0.4s, #24
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; CHECK: sshr v0.4s, v0.4s, #24
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; CHECK: shl v1.4s, v1.4s, #24
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; CHECK: sshr v1.4s, v1.4s, #24
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%1 = sext <4 x i8> %v1 to <4 x i32>
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%2 = sext <4 x i8> %v2 to <4 x i32>
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%3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%4 = trunc <4 x i32> %3 to <4 x i8>
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ret <4 x i8> %4
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}
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define <8 x i8> @test_sext_inreg_v8i8i16(<8 x i8> %v1, <8 x i8> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v8i8i16
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; CHECK: sshll v0.8h, v0.8b, #0
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; CHECK: sshll v1.8h, v1.8b, #0
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%1 = sext <8 x i8> %v1 to <8 x i16>
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%2 = sext <8 x i8> %v2 to <8 x i16>
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%3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%4 = trunc <8 x i16> %3 to <8 x i8>
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ret <8 x i8> %4
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}
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define <8 x i1> @test_sext_inreg_v8i1i16(<8 x i1> %v1, <8 x i1> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v8i1i16
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; CHECK: ushll v1.8h, v1.8b, #0
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; CHECK: ushll v0.8h, v0.8b, #0
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; CHECK: shl v0.8h, v0.8h, #15
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; CHECK: sshr v0.8h, v0.8h, #15
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; CHECK: shl v1.8h, v1.8h, #15
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; CHECK: sshr v1.8h, v1.8h, #15
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%1 = sext <8 x i1> %v1 to <8 x i16>
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%2 = sext <8 x i1> %v2 to <8 x i16>
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%3 = shufflevector <8 x i16> %1, <8 x i16> %2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%4 = trunc <8 x i16> %3 to <8 x i1>
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ret <8 x i1> %4
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}
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define <2 x i16> @test_sext_inreg_v2i16i32(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i16i32
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; CHECK: sshll v0.4s, v0.4h, #0
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; CHECK-NEXT: uzp1 v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: sshll v1.4s, v1.4h, #0
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; CHECK-NEXT: uzp1 v1.4s, v1.4s, v1.4s
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%1 = sext <2 x i16> %v1 to <2 x i32>
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%2 = sext <2 x i16> %v2 to <2 x i32>
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%3 = shufflevector <2 x i32> %1, <2 x i32> %2, <2 x i32> <i32 0, i32 2>
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%4 = trunc <2 x i32> %3 to <2 x i16>
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ret <2 x i16> %4
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}
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define <2 x i16> @test_sext_inreg_v2i16i32_2(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i16i32_2
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; CHECK: sshll v0.4s, v0.4h, #0
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; CHECK-NEXT: uzp1 v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: sshll v1.4s, v1.4h, #0
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; CHECK-NEXT: uzp1 v1.4s, v1.4s, v1.4s
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%a1 = shl <2 x i32> %v1, <i32 16, i32 16>
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%a2 = ashr <2 x i32> %a1, <i32 16, i32 16>
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%b1 = shl <2 x i32> %v2, <i32 16, i32 16>
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%b2 = ashr <2 x i32> %b1, <i32 16, i32 16>
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%c = shufflevector <2 x i32> %a2, <2 x i32> %b2, <2 x i32> <i32 0, i32 2>
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%d = trunc <2 x i32> %c to <2 x i16>
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ret <2 x i16> %d
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}
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define <2 x i16> @test_sext_inreg_v2i16i64(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i16i64
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; CHECK: ushll v1.2d, v1.2s, #0
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; CHECK: ushll v0.2d, v0.2s, #0
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; CHECK: shl v0.2d, v0.2d, #48
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; CHECK: sshr v0.2d, v0.2d, #48
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; CHECK: shl v1.2d, v1.2d, #48
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; CHECK: sshr v1.2d, v1.2d, #48
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%1 = sext <2 x i16> %v1 to <2 x i64>
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%2 = sext <2 x i16> %v2 to <2 x i64>
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%3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 2>
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%4 = trunc <2 x i64> %3 to <2 x i16>
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ret <2 x i16> %4
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}
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define <4 x i16> @test_sext_inreg_v4i16i32(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v4i16i32
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; CHECK: sshll v0.4s, v0.4h, #0
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; CHECK: sshll v1.4s, v1.4h, #0
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%1 = sext <4 x i16> %v1 to <4 x i32>
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%2 = sext <4 x i16> %v2 to <4 x i32>
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%3 = shufflevector <4 x i32> %1, <4 x i32> %2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%4 = trunc <4 x i32> %3 to <4 x i16>
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ret <4 x i16> %4
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}
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define <2 x i32> @test_sext_inreg_v2i32i64(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
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; CHECK-LABEL: test_sext_inreg_v2i32i64
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; CHECK: sshll v0.2d, v0.2s, #0
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; CHECK: sshll v1.2d, v1.2s, #0
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%1 = sext <2 x i32> %v1 to <2 x i64>
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%2 = sext <2 x i32> %v2 to <2 x i64>
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%3 = shufflevector <2 x i64> %1, <2 x i64> %2, <2 x i32> <i32 0, i32 2>
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%4 = trunc <2 x i64> %3 to <2 x i32>
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ret <2 x i32> %4
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}
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