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https://github.com/c64scene-ar/llvm-6502.git
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4210da7253
for the existing instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174389 91177308-0d34-0410-b5e6-96231b3b80d8
35 lines
929 B
LLVM
35 lines
929 B
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; Check that we generate compare to general register.
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define i32 @compare1(i32 %a) nounwind {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}cmp.eq(r{{[0-9]+}},{{ *}}#120)
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entry:
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%cmp = icmp eq i32 %a, 120
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @compare2(i32 %a) nounwind readnone {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}#120)
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entry:
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%cmp = icmp ne i32 %a, 120
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @compare3(i32 %a, i32 %b) nounwind readnone {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
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entry:
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%cmp = icmp eq i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i32 @compare4(i32 %a, i32 %b) nounwind readnone {
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}!cmp.eq(r{{[0-9]+}},{{ *}}r{{[0-9]+}})
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entry:
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%cmp = icmp ne i32 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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