..
Alpha
The dag isel generator generates this now
2005-10-25 20:36:10 +00:00
CBackend
fix CBackend/2005-09-27-VolatileFuncPtr.ll
2005-09-27 20:52:44 +00:00
IA64
Don't generate operations that aren't yet supported
2005-10-21 01:52:45 +00:00
PowerPC
Add a note about some bitfield stuff we could be doing better.
2005-10-25 23:50:02 +00:00
Skeleton
CR registers are not used by this "target"
2005-09-30 06:43:58 +00:00
Sparc
do not wrap this whole file in namespace llvm
2005-10-24 06:38:35 +00:00
SparcV8
do not wrap this whole file in namespace llvm
2005-10-24 06:38:35 +00:00
SparcV9
There is no need to build an archive version of this library
2005-10-24 02:09:03 +00:00
X86
add a note that Nate mentioned last week
2005-10-23 21:44:59 +00:00
Makefile
DONT_BUILD_RELINKED is gone and implied by BUILD_ARCHIVE now
2005-10-24 02:26:13 +00:00
MRegisterInfo.cpp
Rename MRegisterDesc -> TargetRegisterDesc for consistency
2005-09-30 17:49:27 +00:00
SubtargetFeature.cpp
Preparation of supporting scheduling info. Need to find info based on selected
2005-10-25 15:15:28 +00:00
Target.td
Plugin new subtarget backend into the build.
2005-10-21 19:05:19 +00:00
TargetData.cpp
Update to use the new MathExtras.h support for log2 computation.
2005-08-02 19:26:06 +00:00
TargetFrameInfo.cpp
Eliminate all remaining tabs and trailing spaces.
2005-07-27 06:12:32 +00:00
TargetInstrInfo.cpp
Convert tabs to spaces
2005-04-22 17:54:37 +00:00
TargetMachine.cpp
Remove the X86 and PowerPC Simple instruction selectors; their time has
2005-08-18 23:53:15 +00:00
TargetMachineRegistry.cpp
1. Use SubtargetFeatures in llc/lli.
2005-09-01 21:38:21 +00:00
TargetSchedInfo.cpp
Convert tabs to spaces
2005-04-22 17:54:37 +00:00
TargetSchedule.td
add a marker
2005-10-23 22:07:20 +00:00
TargetSelectionDAG.td
Add nodes for CondCodeSDNode and setcc, and add a bunch of pattern fragments
2005-10-26 17:00:25 +00:00
TargetSubtarget.cpp
Eliminate all remaining tabs and trailing spaces.
2005-07-27 06:12:32 +00:00