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llvm-6502/lib/Target/R600
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Matt Arsenault 4aee5942c3 R600: Check if a sextload should be used for parameter loads. 
Through some oddity where truncate (sextload x) isn't folded into
an anyextload for vectors, the sextload remains if the
vector isn't immediately scalarized. This keeps the expected
zextload instructions in the kernel-args test when small type
vectors aren't scalarized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206070 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-11 20:59:54 +00:00
..
InstPrinter Make methods static 2014-03-17 22:23:09 +00:00
MCTargetDesc LLVMBuild.txt: Add missing dependencies. 2014-04-10 11:16:47 +00:00
TargetInfo
AMDGPU.h
AMDGPU.td
AMDGPUAsmPrinter.cpp R600/SI: Use correct dest register class for V_READFIRSTLANE_B32 2014-03-17 17:03:51 +00:00
AMDGPUAsmPrinter.h
AMDGPUCallingConv.td
AMDGPUConvertToISA.cpp
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp Fix indentation 2014-03-11 00:01:27 +00:00
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
AMDGPUInstructions.td R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
AMDGPUIntrinsics.td R600: Add BFE, BFI, and BFM intrinsics to help with writing tests. 2014-03-31 18:21:18 +00:00
AMDGPUISelDAGToDAG.cpp R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
AMDGPUISelLowering.cpp Move ExtractVectorElements to SelectionDAG. 2014-04-11 17:47:30 +00:00
AMDGPUISelLowering.h Move ExtractVectorElements to SelectionDAG. 2014-04-11 17:47:30 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp MachineInstr: introduce explicit_operands and implicit_operands ranges 2014-04-05 22:42:04 +00:00
AMDGPUMCInstLower.h
AMDGPURegisterInfo.cpp Make consistent use of MCPhysReg instead of uint16_t throughout the tree. 2014-04-04 05:16:06 +00:00
AMDGPURegisterInfo.h Make consistent use of MCPhysReg instead of uint16_t throughout the tree. 2014-04-04 05:16:06 +00:00
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp
AMDGPUSubtarget.h R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
AMDGPUTargetMachine.cpp R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU() 2014-03-21 15:51:57 +00:00
AMDGPUTargetMachine.h
AMDGPUTargetTransformInfo.cpp Fix tabs 2014-04-04 20:13:08 +00:00
AMDILBase.td
AMDILCFGStructurizer.cpp Implement depth_first and inverse_depth_first range factory functions. 2014-04-11 01:50:01 +00:00
AMDILInstrInfo.td
AMDILIntrinsicInfo.cpp
AMDILIntrinsicInfo.h
AMDILIntrinsics.td R600: Match sign_extend_inreg to BFE instructions 2014-03-17 18:58:11 +00:00
AMDILISelLowering.cpp R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp 2014-03-25 18:18:27 +00:00
AMDILRegisterInfo.td
CaymanInstructions.td R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
CMakeLists.txt
EvergreenInstructions.td R600: Match 24-bit arithmetic patterns in a Target DAGCombine 2014-04-07 19:45:41 +00:00
LLVMBuild.txt
Makefile
Processors.td
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td R600: Reorganize tablegen instruction definitions 2014-03-24 16:07:25 +00:00
R600Intrinsics.td
R600ISelLowering.cpp R600: Check if a sextload should be used for parameter loads. 2014-04-11 20:59:54 +00:00
R600ISelLowering.h R600/SI: Fix unreachable with a sext_in_reg to an illegal type. 2014-03-27 17:23:24 +00:00
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing 2014-03-13 23:12:04 +00:00
R600Packetizer.cpp
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td R600: Reorganize tablegen instruction definitions 2014-03-24 16:07:25 +00:00
SIAnnotateControlFlow.cpp
SIDefines.h
SIFixSGPRCopies.cpp R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopies 2014-04-07 19:45:45 +00:00
SIInsertWaits.cpp
SIInstrFormats.td R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU() 2014-03-21 15:51:57 +00:00
SIInstrInfo.cpp R600/SI: Refactor SOPC classes slightly. 2014-04-11 19:25:18 +00:00
SIInstrInfo.h R600/SI: Implement shouldConvertConstantLoadToIntImm 2014-03-31 19:54:27 +00:00
SIInstrInfo.td R600/SI: Refactor SOPC classes slightly. 2014-04-11 19:25:18 +00:00
SIInstructions.td R600/SI: Refactor SOPC classes slightly. 2014-04-11 19:25:18 +00:00
SIIntrinsics.td
SIISelLowering.cpp R600: Check if a sextload should be used for parameter loads. 2014-04-11 20:59:54 +00:00
SIISelLowering.h R600: Check if a sextload should be used for parameter loads. 2014-04-11 20:59:54 +00:00
SILowerControlFlow.cpp R600: avoid calling std::next on an iterator that might be end() 2014-03-28 13:52:56 +00:00
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIRegisterInfo.cpp R600/SI: Return the correct index for VGPRs in getHWRegIndex() 2014-03-31 14:01:52 +00:00
SIRegisterInfo.h
SIRegisterInfo.td R600/SI: Use correct dest register class for V_READFIRSTLANE_B32 2014-03-17 17:03:51 +00:00
SISchedule.td
SITypeRewriter.cpp