mirror of
https://github.com/c64scene-ar/llvm-6502.git
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b4186e0ccd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12572 91177308-0d34-0410-b5e6-96231b3b80d8
1412 lines
56 KiB
C++
1412 lines
56 KiB
C++
//===-- PhyRegAlloc.cpp ---------------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Traditional graph-coloring global register allocator currently used
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// by the SPARC back-end.
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//
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// NOTE: This register allocator has some special support
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// for the Reoptimizer, such as not saving some registers on calls to
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// the first-level instrumentation function.
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//
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// NOTE 2: This register allocator can save its state in a global
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// variable in the module it's working on. This feature is not
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// thread-safe; if you have doubts, leave it turned off.
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//
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//===----------------------------------------------------------------------===//
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#include "AllocInfo.h"
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#include "IGNode.h"
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#include "PhyRegAlloc.h"
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#include "RegAllocCommon.h"
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#include "RegClass.h"
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#include "../LiveVar/FunctionLiveVarInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/iOther.h"
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#include "llvm/Module.h"
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#include "llvm/Type.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "../MachineInstrAnnot.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/InstIterator.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "Support/CommandLine.h"
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#include "Support/SetOperations.h"
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#include "Support/STLExtras.h"
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#include <cmath>
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namespace llvm {
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RegAllocDebugLevel_t DEBUG_RA;
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static cl::opt<RegAllocDebugLevel_t, true>
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DRA_opt("dregalloc", cl::Hidden, cl::location(DEBUG_RA),
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cl::desc("enable register allocation debugging information"),
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cl::values(
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clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
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clEnumValN(RA_DEBUG_Results, "y", "debug output for allocation results"),
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clEnumValN(RA_DEBUG_Coloring, "c", "debug output for graph coloring step"),
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clEnumValN(RA_DEBUG_Interference,"ig","debug output for interference graphs"),
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clEnumValN(RA_DEBUG_LiveRanges , "lr","debug output for live ranges"),
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clEnumValN(RA_DEBUG_Verbose, "v", "extra debug output"),
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0));
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/// The reoptimizer wants to be able to grovel through the register
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/// allocator's state after it has done its job. This is a hack.
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///
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PhyRegAlloc::SavedStateMapTy ExportedFnAllocState;
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bool SaveRegAllocState = false;
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bool SaveStateToModule = true;
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static cl::opt<bool, true>
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SaveRegAllocStateOpt("save-ra-state", cl::Hidden,
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cl::location (SaveRegAllocState),
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cl::init(false),
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cl::desc("write reg. allocator state into module"));
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FunctionPass *getRegisterAllocator(TargetMachine &T) {
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return new PhyRegAlloc (T);
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}
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void PhyRegAlloc::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<LoopInfo> ();
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AU.addRequired<FunctionLiveVarInfo> ();
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}
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/// Initialize interference graphs (one in each reg class) and IGNodeLists
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/// (one in each IG). The actual nodes will be pushed later.
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///
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void PhyRegAlloc::createIGNodeListsAndIGs() {
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if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "Creating LR lists ...\n";
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LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
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LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
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for (; HMI != HMIEnd ; ++HMI ) {
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if (HMI->first) {
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LiveRange *L = HMI->second; // get the LiveRange
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if (!L) {
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if (DEBUG_RA && !isa<ConstantIntegral> (HMI->first))
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std::cerr << "\n**** ?!?WARNING: NULL LIVE RANGE FOUND FOR: "
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<< RAV(HMI->first) << "****\n";
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continue;
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}
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// if the Value * is not null, and LR is not yet written to the IGNodeList
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if (!(L->getUserIGNode()) ) {
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RegClass *const RC = // RegClass of first value in the LR
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RegClassList[ L->getRegClassID() ];
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RC->addLRToIG(L); // add this LR to an IG
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}
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}
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}
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// init RegClassList
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for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[rc]->createInterferenceGraph();
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if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "LRLists Created!\n";
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}
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/// Add all interferences for a given instruction. Interference occurs only
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/// if the LR of Def (Inst or Arg) is of the same reg class as that of live
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/// var. The live var passed to this function is the LVset AFTER the
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/// instruction.
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///
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void PhyRegAlloc::addInterference(const Value *Def, const ValueSet *LVSet,
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bool isCallInst) {
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ValueSet::const_iterator LIt = LVSet->begin();
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// get the live range of instruction
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const LiveRange *const LROfDef = LRI->getLiveRangeForValue( Def );
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IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
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assert( IGNodeOfDef );
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RegClass *const RCOfDef = LROfDef->getRegClass();
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// for each live var in live variable set
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for ( ; LIt != LVSet->end(); ++LIt) {
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if (DEBUG_RA >= RA_DEBUG_Verbose)
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std::cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
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// get the live range corresponding to live var
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LiveRange *LROfVar = LRI->getLiveRangeForValue(*LIt);
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// LROfVar can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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if (LROfVar)
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if (LROfDef != LROfVar) // do not set interf for same LR
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if (RCOfDef == LROfVar->getRegClass()) // 2 reg classes are the same
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RCOfDef->setInterference( LROfDef, LROfVar);
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}
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}
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/// For a call instruction, this method sets the CallInterference flag in
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/// the LR of each variable live in the Live Variable Set live after the
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/// call instruction (except the return value of the call instruction - since
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/// the return value does not interfere with that call itself).
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///
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void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
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const ValueSet *LVSetAft) {
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if (DEBUG_RA >= RA_DEBUG_Interference)
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std::cerr << "\n For call inst: " << *MInst;
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// for each live var in live variable set after machine inst
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for (ValueSet::const_iterator LIt = LVSetAft->begin(), LEnd = LVSetAft->end();
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LIt != LEnd; ++LIt) {
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// get the live range corresponding to live var
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LiveRange *const LR = LRI->getLiveRangeForValue(*LIt );
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// LR can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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if (LR ) {
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if (DEBUG_RA >= RA_DEBUG_Interference) {
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std::cerr << "\n\tLR after Call: ";
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printSet(*LR);
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}
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LR->setCallInterference();
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if (DEBUG_RA >= RA_DEBUG_Interference) {
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std::cerr << "\n ++After adding call interference for LR: " ;
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printSet(*LR);
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}
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}
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}
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// Now find the LR of the return value of the call
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// We do this because, we look at the LV set *after* the instruction
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// to determine, which LRs must be saved across calls. The return value
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// of the call is live in this set - but it does not interfere with call
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// (i.e., we can allocate a volatile register to the return value)
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CallArgsDescriptor* argDesc = CallArgsDescriptor::get(MInst);
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if (const Value *RetVal = argDesc->getReturnValue()) {
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LiveRange *RetValLR = LRI->getLiveRangeForValue( RetVal );
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assert( RetValLR && "No LR for RetValue of call");
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RetValLR->clearCallInterference();
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}
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// If the CALL is an indirect call, find the LR of the function pointer.
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// That has a call interference because it conflicts with outgoing args.
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if (const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
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LiveRange *AddrValLR = LRI->getLiveRangeForValue( AddrVal );
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assert( AddrValLR && "No LR for indirect addr val of call");
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AddrValLR->setCallInterference();
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}
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}
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/// Create interferences in the IG of each RegClass, and calculate the spill
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/// cost of each Live Range (it is done in this method to save another pass
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/// over the code).
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///
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void PhyRegAlloc::buildInterferenceGraphs() {
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if (DEBUG_RA >= RA_DEBUG_Interference)
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std::cerr << "Creating interference graphs ...\n";
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unsigned BBLoopDepthCost;
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for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
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BBI != BBE; ++BBI) {
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const MachineBasicBlock &MBB = *BBI;
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const BasicBlock *BB = MBB.getBasicBlock();
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// find the 10^(loop_depth) of this BB
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BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BB));
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// get the iterator for machine instructions
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MachineBasicBlock::const_iterator MII = MBB.begin();
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// iterate over all the machine instructions in BB
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for ( ; MII != MBB.end(); ++MII) {
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const MachineInstr *MInst = MII;
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// get the LV set after the instruction
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const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
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bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpcode());
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if (isCallInst) {
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// set the isCallInterference flag of each live range which extends
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// across this call instruction. This information is used by graph
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// coloring algorithm to avoid allocating volatile colors to live ranges
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// that span across calls (since they have to be saved/restored)
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setCallInterferences(MInst, &LVSetAI);
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}
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// iterate over all MI operands to find defs
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for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
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OpE = MInst->end(); OpI != OpE; ++OpI) {
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if (OpI.isDef()) // create a new LR since def
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addInterference(*OpI, &LVSetAI, isCallInst);
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// Calculate the spill cost of each live range
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LiveRange *LR = LRI->getLiveRangeForValue(*OpI);
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if (LR) LR->addSpillCost(BBLoopDepthCost);
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}
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// Mark all operands of pseudo-instructions as interfering with one
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// another. This must be done because pseudo-instructions may be
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// expanded to multiple instructions by the assembler, so all the
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// operands must get distinct registers.
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if (TM.getInstrInfo().isPseudoInstr(MInst->getOpcode()))
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addInterf4PseudoInstr(MInst);
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// Also add interference for any implicit definitions in a machine
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// instr (currently, only calls have this).
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unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
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for (unsigned z=0; z < NumOfImpRefs; z++)
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if (MInst->getImplicitOp(z).isDef())
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addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
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} // for all machine instructions in BB
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} // for all BBs in function
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// add interferences for function arguments. Since there are no explicit
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// defs in the function for args, we have to add them manually
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addInterferencesForArgs();
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if (DEBUG_RA >= RA_DEBUG_Interference)
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std::cerr << "Interference graphs calculated!\n";
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}
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/// Mark all operands of the given MachineInstr as interfering with one
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/// another.
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///
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void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
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bool setInterf = false;
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// iterate over MI operands to find defs
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for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
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ItE = MInst->end(); It1 != ItE; ++It1) {
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const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1);
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assert((LROfOp1 || It1.isDef()) && "No LR for Def in PSEUDO insruction");
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MachineInstr::const_val_op_iterator It2 = It1;
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for (++It2; It2 != ItE; ++It2) {
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const LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2);
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if (LROfOp2) {
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RegClass *RCOfOp1 = LROfOp1->getRegClass();
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RegClass *RCOfOp2 = LROfOp2->getRegClass();
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if (RCOfOp1 == RCOfOp2 ){
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RCOfOp1->setInterference( LROfOp1, LROfOp2 );
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setInterf = true;
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}
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} // if Op2 has a LR
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} // for all other defs in machine instr
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} // for all operands in an instruction
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if (!setInterf && MInst->getNumOperands() > 2) {
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std::cerr << "\nInterf not set for any operand in pseudo instr:\n";
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std::cerr << *MInst;
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assert(0 && "Interf not set for pseudo instr with > 2 operands" );
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}
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}
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/// Add interferences for incoming arguments to a function.
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///
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void PhyRegAlloc::addInterferencesForArgs() {
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// get the InSet of root BB
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const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
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for (Function::const_aiterator AI = Fn->abegin(); AI != Fn->aend(); ++AI) {
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// add interferences between args and LVars at start
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addInterference(AI, &InSet, false);
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if (DEBUG_RA >= RA_DEBUG_Interference)
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std::cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
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}
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}
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/// The following are utility functions used solely by updateMachineCode and
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/// the functions that it calls. They should probably be folded back into
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/// updateMachineCode at some point.
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///
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// used by: updateMachineCode (1 time), PrependInstructions (1 time)
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inline void InsertBefore(MachineInstr* newMI, MachineBasicBlock& MBB,
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MachineBasicBlock::iterator& MII) {
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MII = MBB.insert(MII, newMI);
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++MII;
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}
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// used by: AppendInstructions (1 time)
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inline void InsertAfter(MachineInstr* newMI, MachineBasicBlock& MBB,
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MachineBasicBlock::iterator& MII) {
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++MII; // insert before the next instruction
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MII = MBB.insert(MII, newMI);
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}
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// used by: updateMachineCode (2 times)
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inline void PrependInstructions(std::vector<MachineInstr *> &IBef,
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MachineBasicBlock& MBB,
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MachineBasicBlock::iterator& MII,
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const std::string& msg) {
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if (!IBef.empty()) {
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MachineInstr* OrigMI = MII;
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std::vector<MachineInstr *>::iterator AdIt;
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for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt) {
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if (DEBUG_RA) {
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if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
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std::cerr << msg << "PREPENDed instr:\n " << **AdIt << "\n";
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}
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InsertBefore(*AdIt, MBB, MII);
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}
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}
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}
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// used by: updateMachineCode (1 time)
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inline void AppendInstructions(std::vector<MachineInstr *> &IAft,
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MachineBasicBlock& MBB,
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MachineBasicBlock::iterator& MII,
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const std::string& msg) {
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if (!IAft.empty()) {
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MachineInstr* OrigMI = MII;
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std::vector<MachineInstr *>::iterator AdIt;
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for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
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if (DEBUG_RA) {
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if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
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std::cerr << msg << "APPENDed instr:\n " << **AdIt << "\n";
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}
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InsertAfter(*AdIt, MBB, MII);
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}
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}
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}
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/// Set the registers for operands in the given MachineInstr, if a register was
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/// successfully allocated. Return true if any of its operands has been marked
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/// for spill.
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///
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bool PhyRegAlloc::markAllocatedRegs(MachineInstr* MInst)
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{
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bool instrNeedsSpills = false;
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// First, set the registers for operands in the machine instruction
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// if a register was successfully allocated. Do this first because we
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// will need to know which registers are already used by this instr'n.
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for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
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MachineOperand& Op = MInst->getOperand(OpNum);
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if (Op.getType() == MachineOperand::MO_VirtualRegister ||
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Op.getType() == MachineOperand::MO_CCRegister) {
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const Value *const Val = Op.getVRegValue();
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if (const LiveRange* LR = LRI->getLiveRangeForValue(Val)) {
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// Remember if any operand needs spilling
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instrNeedsSpills |= LR->isMarkedForSpill();
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// An operand may have a color whether or not it needs spilling
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if (LR->hasColor())
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MInst->SetRegForOperand(OpNum,
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MRI.getUnifiedRegNum(LR->getRegClassID(),
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LR->getColor()));
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}
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}
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} // for each operand
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return instrNeedsSpills;
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}
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/// Mark allocated registers (using markAllocatedRegs()) on the instruction
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/// that MII points to. Then, if it's a call instruction, insert caller-saving
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/// code before and after it. Finally, insert spill code before and after it,
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/// using insertCode4SpilledLR().
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///
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void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
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MachineBasicBlock &MBB) {
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MachineInstr* MInst = MII;
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unsigned Opcode = MInst->getOpcode();
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// Reset tmp stack positions so they can be reused for each machine instr.
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MF->getInfo()->popAllTempValues();
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// Mark the operands for which regs have been allocated.
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bool instrNeedsSpills = markAllocatedRegs(MII);
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#ifndef NDEBUG
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// Mark that the operands have been updated. Later,
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// setRelRegsUsedByThisInst() is called to find registers used by each
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// MachineInst, and it should not be used for an instruction until
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// this is done. This flag just serves as a sanity check.
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OperandsColoredMap[MInst] = true;
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#endif
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// Now insert caller-saving code before/after the call.
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// Do this before inserting spill code since some registers must be
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// used by save/restore and spill code should not use those registers.
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if (TM.getInstrInfo().isCall(Opcode)) {
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AddedInstrns &AI = AddedInstrMap[MInst];
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insertCallerSavingCode(AI.InstrnsBefore, AI.InstrnsAfter, MInst,
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MBB.getBasicBlock());
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}
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|
|
// Now insert spill code for remaining operands not allocated to
|
|
// registers. This must be done even for call return instructions
|
|
// since those are not handled by the special code above.
|
|
if (instrNeedsSpills)
|
|
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
|
|
MachineOperand& Op = MInst->getOperand(OpNum);
|
|
if (Op.getType() == MachineOperand::MO_VirtualRegister ||
|
|
Op.getType() == MachineOperand::MO_CCRegister) {
|
|
const Value* Val = Op.getVRegValue();
|
|
if (const LiveRange *LR = LRI->getLiveRangeForValue(Val))
|
|
if (LR->isMarkedForSpill())
|
|
insertCode4SpilledLR(LR, MII, MBB, OpNum);
|
|
}
|
|
} // for each operand
|
|
}
|
|
|
|
/// Iterate over all the MachineBasicBlocks in the current function and set
|
|
/// the allocated registers for each instruction (using updateInstruction()),
|
|
/// after register allocation is complete. Then move code out of delay slots.
|
|
///
|
|
void PhyRegAlloc::updateMachineCode()
|
|
{
|
|
// Insert any instructions needed at method entry
|
|
MachineBasicBlock::iterator MII = MF->front().begin();
|
|
PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MF->front(), MII,
|
|
"At function entry: \n");
|
|
assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
|
|
"InstrsAfter should be unnecessary since we are just inserting at "
|
|
"the function entry point here.");
|
|
|
|
for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
|
|
BBI != BBE; ++BBI) {
|
|
MachineBasicBlock &MBB = *BBI;
|
|
|
|
// Iterate over all machine instructions in BB and mark operands with
|
|
// their assigned registers or insert spill code, as appropriate.
|
|
// Also, fix operands of call/return instructions.
|
|
for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
|
|
if (! TM.getInstrInfo().isDummyPhiInstr(MII->getOpcode()))
|
|
updateInstruction(MII, MBB);
|
|
|
|
// Now, move code out of delay slots of branches and returns if needed.
|
|
// (Also, move "after" code from calls to the last delay slot instruction.)
|
|
// Moving code out of delay slots is needed in 2 situations:
|
|
// (1) If this is a branch and it needs instructions inserted after it,
|
|
// move any existing instructions out of the delay slot so that the
|
|
// instructions can go into the delay slot. This only supports the
|
|
// case that #instrsAfter <= #delay slots.
|
|
//
|
|
// (2) If any instruction in the delay slot needs
|
|
// instructions inserted, move it out of the delay slot and before the
|
|
// branch because putting code before or after it would be VERY BAD!
|
|
//
|
|
// If the annul bit of the branch is set, neither of these is legal!
|
|
// If so, we need to handle spill differently but annulling is not yet used.
|
|
for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
|
|
if (unsigned delaySlots =
|
|
TM.getInstrInfo().getNumDelaySlots(MII->getOpcode())) {
|
|
MachineBasicBlock::iterator DelaySlotMI = next(MII);
|
|
assert(DelaySlotMI != MBB.end() && "no instruction for delay slot");
|
|
|
|
// Check the 2 conditions above:
|
|
// (1) Does a branch need instructions added after it?
|
|
// (2) O/w does delay slot instr. need instrns before or after?
|
|
bool isBranch = (TM.getInstrInfo().isBranch(MII->getOpcode()) ||
|
|
TM.getInstrInfo().isReturn(MII->getOpcode()));
|
|
bool cond1 = (isBranch &&
|
|
AddedInstrMap.count(MII) &&
|
|
AddedInstrMap[MII].InstrnsAfter.size() > 0);
|
|
bool cond2 = (AddedInstrMap.count(DelaySlotMI) &&
|
|
(AddedInstrMap[DelaySlotMI].InstrnsBefore.size() > 0 ||
|
|
AddedInstrMap[DelaySlotMI].InstrnsAfter.size() > 0));
|
|
|
|
if (cond1 || cond2) {
|
|
assert(delaySlots==1 &&
|
|
"InsertBefore does not yet handle >1 delay slots!");
|
|
|
|
if (DEBUG_RA) {
|
|
std::cerr << "\nRegAlloc: Moved instr. with added code: "
|
|
<< *DelaySlotMI
|
|
<< " out of delay slots of instr: " << *MII;
|
|
}
|
|
|
|
// move instruction before branch
|
|
MBB.insert(MII, MBB.remove(DelaySlotMI++));
|
|
|
|
// On cond1 we are done (we already moved the
|
|
// instruction out of the delay slot). On cond2 we need
|
|
// to insert a nop in place of the moved instruction
|
|
if (cond2) {
|
|
MBB.insert(MII, BuildMI(TM.getInstrInfo().getNOPOpCode(),1));
|
|
}
|
|
}
|
|
else {
|
|
// For non-branch instr with delay slots (probably a call), move
|
|
// InstrAfter to the instr. in the last delay slot.
|
|
MachineBasicBlock::iterator tmp = next(MII, delaySlots);
|
|
move2DelayedInstr(MII, tmp);
|
|
}
|
|
}
|
|
|
|
// Finally iterate over all instructions in BB and insert before/after
|
|
for (MachineBasicBlock::iterator MII=MBB.begin(); MII != MBB.end(); ++MII) {
|
|
MachineInstr *MInst = MII;
|
|
|
|
// do not process Phis
|
|
if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpcode()))
|
|
continue;
|
|
|
|
// if there are any added instructions...
|
|
if (AddedInstrMap.count(MInst)) {
|
|
AddedInstrns &CallAI = AddedInstrMap[MInst];
|
|
|
|
#ifndef NDEBUG
|
|
bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpcode()) ||
|
|
TM.getInstrInfo().isReturn(MInst->getOpcode()));
|
|
assert((!isBranch ||
|
|
AddedInstrMap[MInst].InstrnsAfter.size() <=
|
|
TM.getInstrInfo().getNumDelaySlots(MInst->getOpcode())) &&
|
|
"Cannot put more than #delaySlots instrns after "
|
|
"branch or return! Need to handle temps differently.");
|
|
#endif
|
|
|
|
#ifndef NDEBUG
|
|
// Temporary sanity checking code to detect whether the same machine
|
|
// instruction is ever inserted twice before/after a call.
|
|
// I suspect this is happening but am not sure. --Vikram, 7/1/03.
|
|
std::set<const MachineInstr*> instrsSeen;
|
|
for (int i = 0, N = CallAI.InstrnsBefore.size(); i < N; ++i) {
|
|
assert(instrsSeen.count(CallAI.InstrnsBefore[i]) == 0 &&
|
|
"Duplicate machine instruction in InstrnsBefore!");
|
|
instrsSeen.insert(CallAI.InstrnsBefore[i]);
|
|
}
|
|
for (int i = 0, N = CallAI.InstrnsAfter.size(); i < N; ++i) {
|
|
assert(instrsSeen.count(CallAI.InstrnsAfter[i]) == 0 &&
|
|
"Duplicate machine instruction in InstrnsBefore/After!");
|
|
instrsSeen.insert(CallAI.InstrnsAfter[i]);
|
|
}
|
|
#endif
|
|
|
|
// Now add the instructions before/after this MI.
|
|
// We do this here to ensure that spill for an instruction is inserted
|
|
// as close as possible to an instruction (see above insertCode4Spill)
|
|
if (! CallAI.InstrnsBefore.empty())
|
|
PrependInstructions(CallAI.InstrnsBefore, MBB, MII,"");
|
|
|
|
if (! CallAI.InstrnsAfter.empty())
|
|
AppendInstructions(CallAI.InstrnsAfter, MBB, MII,"");
|
|
|
|
} // if there are any added instructions
|
|
} // for each machine instruction
|
|
}
|
|
}
|
|
|
|
|
|
/// Insert spill code for AN operand whose LR was spilled. May be called
|
|
/// repeatedly for a single MachineInstr if it has many spilled operands. On
|
|
/// each call, it finds a register which is not live at that instruction and
|
|
/// also which is not used by other spilled operands of the same
|
|
/// instruction. Then it uses this register temporarily to accommodate the
|
|
/// spilled value.
|
|
///
|
|
void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
|
|
MachineBasicBlock::iterator& MII,
|
|
MachineBasicBlock &MBB,
|
|
const unsigned OpNum) {
|
|
MachineInstr *MInst = MII;
|
|
const BasicBlock *BB = MBB.getBasicBlock();
|
|
|
|
assert((! TM.getInstrInfo().isCall(MInst->getOpcode()) || OpNum == 0) &&
|
|
"Outgoing arg of a call must be handled elsewhere (func arg ok)");
|
|
assert(! TM.getInstrInfo().isReturn(MInst->getOpcode()) &&
|
|
"Return value of a ret must be handled elsewhere");
|
|
|
|
MachineOperand& Op = MInst->getOperand(OpNum);
|
|
bool isDef = Op.isDef();
|
|
bool isUse = Op.isUse();
|
|
unsigned RegType = MRI.getRegTypeForLR(LR);
|
|
int SpillOff = LR->getSpillOffFromFP();
|
|
RegClass *RC = LR->getRegClass();
|
|
|
|
// Get the live-variable set to find registers free before this instr.
|
|
const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
|
|
|
|
#ifndef NDEBUG
|
|
// If this instr. is in the delay slot of a branch or return, we need to
|
|
// include all live variables before that branch or return -- we don't want to
|
|
// trample those! Verify that the set is included in the LV set before MInst.
|
|
if (MII != MBB.begin()) {
|
|
MachineBasicBlock::iterator PredMI = prior(MII);
|
|
if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpcode()))
|
|
assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
|
|
.empty() && "Live-var set before branch should be included in "
|
|
"live-var set of each delay slot instruction!");
|
|
}
|
|
#endif
|
|
|
|
MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
|
|
|
|
std::vector<MachineInstr*> MIBef, MIAft;
|
|
std::vector<MachineInstr*> AdIMid;
|
|
|
|
// Choose a register to hold the spilled value, if one was not preallocated.
|
|
// This may insert code before and after MInst to free up the value. If so,
|
|
// this code should be first/last in the spill sequence before/after MInst.
|
|
int TmpRegU=(LR->hasColor()
|
|
? MRI.getUnifiedRegNum(LR->getRegClassID(),LR->getColor())
|
|
: getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef,MIAft));
|
|
|
|
// Set the operand first so that it this register does not get used
|
|
// as a scratch register for later calls to getUsableUniRegAtMI below
|
|
MInst->SetRegForOperand(OpNum, TmpRegU);
|
|
|
|
// get the added instructions for this instruction
|
|
AddedInstrns &AI = AddedInstrMap[MInst];
|
|
|
|
// We may need a scratch register to copy the spilled value to/from memory.
|
|
// This may itself have to insert code to free up a scratch register.
|
|
// Any such code should go before (after) the spill code for a load (store).
|
|
// The scratch reg is not marked as used because it is only used
|
|
// for the copy and not used across MInst.
|
|
int scratchRegType = -1;
|
|
int scratchReg = -1;
|
|
if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
|
|
scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
|
|
MInst, MIBef, MIAft);
|
|
assert(scratchReg != MRI.getInvalidRegNum());
|
|
}
|
|
|
|
if (isUse) {
|
|
// for a USE, we have to load the value of LR from stack to a TmpReg
|
|
// and use the TmpReg as one operand of instruction
|
|
|
|
// actual loading instruction(s)
|
|
MRI.cpMem2RegMI(AdIMid, MRI.getFramePointer(), SpillOff, TmpRegU,
|
|
RegType, scratchReg);
|
|
|
|
// the actual load should be after the instructions to free up TmpRegU
|
|
MIBef.insert(MIBef.end(), AdIMid.begin(), AdIMid.end());
|
|
AdIMid.clear();
|
|
}
|
|
|
|
if (isDef) { // if this is a Def
|
|
// for a DEF, we have to store the value produced by this instruction
|
|
// on the stack position allocated for this LR
|
|
|
|
// actual storing instruction(s)
|
|
MRI.cpReg2MemMI(AdIMid, TmpRegU, MRI.getFramePointer(), SpillOff,
|
|
RegType, scratchReg);
|
|
|
|
MIAft.insert(MIAft.begin(), AdIMid.begin(), AdIMid.end());
|
|
} // if !DEF
|
|
|
|
// Finally, insert the entire spill code sequences before/after MInst
|
|
AI.InstrnsBefore.insert(AI.InstrnsBefore.end(), MIBef.begin(), MIBef.end());
|
|
AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft.begin(), MIAft.end());
|
|
|
|
if (DEBUG_RA) {
|
|
std::cerr << "\nFor Inst:\n " << *MInst;
|
|
std::cerr << "SPILLED LR# " << LR->getUserIGNode()->getIndex();
|
|
std::cerr << "; added Instructions:";
|
|
for_each(MIBef.begin(), MIBef.end(), std::mem_fun(&MachineInstr::dump));
|
|
for_each(MIAft.begin(), MIAft.end(), std::mem_fun(&MachineInstr::dump));
|
|
}
|
|
}
|
|
|
|
|
|
/// Insert caller saving/restoring instructions before/after a call machine
|
|
/// instruction (before or after any other instructions that were inserted for
|
|
/// the call).
|
|
///
|
|
void
|
|
PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
|
|
std::vector<MachineInstr*> &instrnsAfter,
|
|
MachineInstr *CallMI,
|
|
const BasicBlock *BB) {
|
|
assert(TM.getInstrInfo().isCall(CallMI->getOpcode()));
|
|
|
|
// hash set to record which registers were saved/restored
|
|
hash_set<unsigned> PushedRegSet;
|
|
|
|
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
|
|
|
|
// if the call is to a instrumentation function, do not insert save and
|
|
// restore instructions the instrumentation function takes care of save
|
|
// restore for volatile regs.
|
|
//
|
|
// FIXME: this should be made general, not specific to the reoptimizer!
|
|
const Function *Callee = argDesc->getCallInst()->getCalledFunction();
|
|
bool isLLVMFirstTrigger = Callee && Callee->getName() == "llvm_first_trigger";
|
|
|
|
// Now check if the call has a return value (using argDesc) and if so,
|
|
// find the LR of the TmpInstruction representing the return value register.
|
|
// (using the last or second-last *implicit operand* of the call MI).
|
|
// Insert it to to the PushedRegSet since we must not save that register
|
|
// and restore it after the call.
|
|
// We do this because, we look at the LV set *after* the instruction
|
|
// to determine, which LRs must be saved across calls. The return value
|
|
// of the call is live in this set - but we must not save/restore it.
|
|
if (const Value *origRetVal = argDesc->getReturnValue()) {
|
|
unsigned retValRefNum = (CallMI->getNumImplicitRefs() -
|
|
(argDesc->getIndirectFuncPtr()? 1 : 2));
|
|
const TmpInstruction* tmpRetVal =
|
|
cast<TmpInstruction>(CallMI->getImplicitRef(retValRefNum));
|
|
assert(tmpRetVal->getOperand(0) == origRetVal &&
|
|
tmpRetVal->getType() == origRetVal->getType() &&
|
|
"Wrong implicit ref?");
|
|
LiveRange *RetValLR = LRI->getLiveRangeForValue(tmpRetVal);
|
|
assert(RetValLR && "No LR for RetValue of call");
|
|
|
|
if (! RetValLR->isMarkedForSpill())
|
|
PushedRegSet.insert(MRI.getUnifiedRegNum(RetValLR->getRegClassID(),
|
|
RetValLR->getColor()));
|
|
}
|
|
|
|
const ValueSet &LVSetAft = LVI->getLiveVarSetAfterMInst(CallMI, BB);
|
|
ValueSet::const_iterator LIt = LVSetAft.begin();
|
|
|
|
// for each live var in live variable set after machine inst
|
|
for( ; LIt != LVSetAft.end(); ++LIt) {
|
|
// get the live range corresponding to live var
|
|
LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
|
|
|
|
// LR can be null if it is a const since a const
|
|
// doesn't have a dominating def - see Assumptions above
|
|
if (LR) {
|
|
if (! LR->isMarkedForSpill()) {
|
|
assert(LR->hasColor() && "LR is neither spilled nor colored?");
|
|
unsigned RCID = LR->getRegClassID();
|
|
unsigned Color = LR->getColor();
|
|
|
|
if (MRI.isRegVolatile(RCID, Color) ) {
|
|
// if this is a call to the first-level reoptimizer
|
|
// instrumentation entry point, and the register is not
|
|
// modified by call, don't save and restore it.
|
|
if (isLLVMFirstTrigger && !MRI.modifiedByCall(RCID, Color))
|
|
continue;
|
|
|
|
// if the value is in both LV sets (i.e., live before and after
|
|
// the call machine instruction)
|
|
unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
|
|
|
|
// if we haven't already pushed this register...
|
|
if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
|
|
unsigned RegType = MRI.getRegTypeForLR(LR);
|
|
|
|
// Now get two instructions - to push on stack and pop from stack
|
|
// and add them to InstrnsBefore and InstrnsAfter of the
|
|
// call instruction
|
|
int StackOff =
|
|
MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
|
|
|
|
//---- Insert code for pushing the reg on stack ----------
|
|
|
|
std::vector<MachineInstr*> AdIBef, AdIAft;
|
|
|
|
// We may need a scratch register to copy the saved value
|
|
// to/from memory. This may itself have to insert code to
|
|
// free up a scratch register. Any such code should go before
|
|
// the save code. The scratch register, if any, is by default
|
|
// temporary and not "used" by the instruction unless the
|
|
// copy code itself decides to keep the value in the scratch reg.
|
|
int scratchRegType = -1;
|
|
int scratchReg = -1;
|
|
if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
|
|
{ // Find a register not live in the LVSet before CallMI
|
|
const ValueSet &LVSetBef =
|
|
LVI->getLiveVarSetBeforeMInst(CallMI, BB);
|
|
scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
|
|
CallMI, AdIBef, AdIAft);
|
|
assert(scratchReg != MRI.getInvalidRegNum());
|
|
}
|
|
|
|
if (AdIBef.size() > 0)
|
|
instrnsBefore.insert(instrnsBefore.end(),
|
|
AdIBef.begin(), AdIBef.end());
|
|
|
|
MRI.cpReg2MemMI(instrnsBefore, Reg, MRI.getFramePointer(),
|
|
StackOff, RegType, scratchReg);
|
|
|
|
if (AdIAft.size() > 0)
|
|
instrnsBefore.insert(instrnsBefore.end(),
|
|
AdIAft.begin(), AdIAft.end());
|
|
|
|
//---- Insert code for popping the reg from the stack ----------
|
|
AdIBef.clear();
|
|
AdIAft.clear();
|
|
|
|
// We may need a scratch register to copy the saved value
|
|
// from memory. This may itself have to insert code to
|
|
// free up a scratch register. Any such code should go
|
|
// after the save code. As above, scratch is not marked "used".
|
|
scratchRegType = -1;
|
|
scratchReg = -1;
|
|
if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
|
|
{ // Find a register not live in the LVSet after CallMI
|
|
scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetAft,
|
|
CallMI, AdIBef, AdIAft);
|
|
assert(scratchReg != MRI.getInvalidRegNum());
|
|
}
|
|
|
|
if (AdIBef.size() > 0)
|
|
instrnsAfter.insert(instrnsAfter.end(),
|
|
AdIBef.begin(), AdIBef.end());
|
|
|
|
MRI.cpMem2RegMI(instrnsAfter, MRI.getFramePointer(), StackOff,
|
|
Reg, RegType, scratchReg);
|
|
|
|
if (AdIAft.size() > 0)
|
|
instrnsAfter.insert(instrnsAfter.end(),
|
|
AdIAft.begin(), AdIAft.end());
|
|
|
|
PushedRegSet.insert(Reg);
|
|
|
|
if(DEBUG_RA) {
|
|
std::cerr << "\nFor call inst:" << *CallMI;
|
|
std::cerr << " -inserted caller saving instrs: Before:\n\t ";
|
|
for_each(instrnsBefore.begin(), instrnsBefore.end(),
|
|
std::mem_fun(&MachineInstr::dump));
|
|
std::cerr << " -and After:\n\t ";
|
|
for_each(instrnsAfter.begin(), instrnsAfter.end(),
|
|
std::mem_fun(&MachineInstr::dump));
|
|
}
|
|
} // if not already pushed
|
|
} // if LR has a volatile color
|
|
} // if LR has color
|
|
} // if there is a LR for Var
|
|
} // for each value in the LV set after instruction
|
|
}
|
|
|
|
|
|
/// Returns the unified register number of a temporary register to be used
|
|
/// BEFORE MInst. If no register is available, it will pick one and modify
|
|
/// MIBef and MIAft to contain instructions used to free up this returned
|
|
/// register.
|
|
///
|
|
int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
|
|
const ValueSet *LVSetBef,
|
|
MachineInstr *MInst,
|
|
std::vector<MachineInstr*>& MIBef,
|
|
std::vector<MachineInstr*>& MIAft) {
|
|
RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
|
|
|
|
int RegU = getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
|
|
|
|
if (RegU == -1) {
|
|
// we couldn't find an unused register. Generate code to free up a reg by
|
|
// saving it on stack and restoring after the instruction
|
|
|
|
int TmpOff = MF->getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
|
|
|
|
RegU = getUniRegNotUsedByThisInst(RC, RegType, MInst);
|
|
|
|
// Check if we need a scratch register to copy this register to memory.
|
|
int scratchRegType = -1;
|
|
if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
|
|
int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
|
|
MInst, MIBef, MIAft);
|
|
assert(scratchReg != MRI.getInvalidRegNum());
|
|
|
|
// We may as well hold the value in the scratch register instead
|
|
// of copying it to memory and back. But we have to mark the
|
|
// register as used by this instruction, so it does not get used
|
|
// as a scratch reg. by another operand or anyone else.
|
|
ScratchRegsUsed.insert(std::make_pair(MInst, scratchReg));
|
|
MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
|
|
MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
|
|
} else { // the register can be copied directly to/from memory so do it.
|
|
MRI.cpReg2MemMI(MIBef, RegU, MRI.getFramePointer(), TmpOff, RegType);
|
|
MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
|
|
}
|
|
}
|
|
|
|
return RegU;
|
|
}
|
|
|
|
|
|
/// Returns the register-class register number of a new unused register that
|
|
/// can be used to accommodate a temporary value. May be called repeatedly
|
|
/// for a single MachineInstr. On each call, it finds a register which is not
|
|
/// live at that instruction and which is not used by any spilled operands of
|
|
/// that instruction.
|
|
///
|
|
int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC, const int RegType,
|
|
const MachineInstr *MInst,
|
|
const ValueSet* LVSetBef) {
|
|
RC->clearColorsUsed(); // Reset array
|
|
|
|
if (LVSetBef == NULL) {
|
|
LVSetBef = &LVI->getLiveVarSetBeforeMInst(MInst);
|
|
assert(LVSetBef != NULL && "Unable to get live-var set before MInst?");
|
|
}
|
|
|
|
ValueSet::const_iterator LIt = LVSetBef->begin();
|
|
|
|
// for each live var in live variable set after machine inst
|
|
for ( ; LIt != LVSetBef->end(); ++LIt) {
|
|
// Get the live range corresponding to live var, and its RegClass
|
|
LiveRange *const LRofLV = LRI->getLiveRangeForValue(*LIt );
|
|
|
|
// LR can be null if it is a const since a const
|
|
// doesn't have a dominating def - see Assumptions above
|
|
if (LRofLV && LRofLV->getRegClass() == RC && LRofLV->hasColor())
|
|
RC->markColorsUsed(LRofLV->getColor(),
|
|
MRI.getRegTypeForLR(LRofLV), RegType);
|
|
}
|
|
|
|
// It is possible that one operand of this MInst was already spilled
|
|
// and it received some register temporarily. If that's the case,
|
|
// it is recorded in machine operand. We must skip such registers.
|
|
setRelRegsUsedByThisInst(RC, RegType, MInst);
|
|
|
|
int unusedReg = RC->getUnusedColor(RegType); // find first unused color
|
|
if (unusedReg >= 0)
|
|
return MRI.getUnifiedRegNum(RC->getID(), unusedReg);
|
|
|
|
return -1;
|
|
}
|
|
|
|
|
|
/// Return the unified register number of a register in class RC which is not
|
|
/// used by any operands of MInst.
|
|
///
|
|
int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
|
|
const int RegType,
|
|
const MachineInstr *MInst) {
|
|
RC->clearColorsUsed();
|
|
|
|
setRelRegsUsedByThisInst(RC, RegType, MInst);
|
|
|
|
// find the first unused color
|
|
int unusedReg = RC->getUnusedColor(RegType);
|
|
assert(unusedReg >= 0 &&
|
|
"FATAL: No free register could be found in reg class!!");
|
|
|
|
return MRI.getUnifiedRegNum(RC->getID(), unusedReg);
|
|
}
|
|
|
|
|
|
/// Modify the IsColorUsedArr of register class RC, by setting the bits
|
|
/// corresponding to register RegNo. This is a helper method of
|
|
/// setRelRegsUsedByThisInst().
|
|
///
|
|
static void markRegisterUsed(int RegNo, RegClass *RC, int RegType,
|
|
const TargetRegInfo &TRI) {
|
|
unsigned classId = 0;
|
|
int classRegNum = TRI.getClassRegNum(RegNo, classId);
|
|
if (RC->getID() == classId)
|
|
RC->markColorsUsed(classRegNum, RegType, RegType);
|
|
}
|
|
|
|
void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
|
|
const MachineInstr *MI) {
|
|
assert(OperandsColoredMap[MI] == true &&
|
|
"Illegal to call setRelRegsUsedByThisInst() until colored operands "
|
|
"are marked for an instruction.");
|
|
|
|
// Add the registers already marked as used by the instruction. Both
|
|
// explicit and implicit operands are set.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
|
|
if (MI->getOperand(i).hasAllocatedReg())
|
|
markRegisterUsed(MI->getOperand(i).getReg(), RC, RegType,MRI);
|
|
|
|
for (unsigned i = 0, e = MI->getNumImplicitRefs(); i != e; ++i)
|
|
if (MI->getImplicitOp(i).hasAllocatedReg())
|
|
markRegisterUsed(MI->getImplicitOp(i).getReg(), RC, RegType,MRI);
|
|
|
|
// Add all of the scratch registers that are used to save values across the
|
|
// instruction (e.g., for saving state register values).
|
|
std::pair<ScratchRegsUsedTy::iterator, ScratchRegsUsedTy::iterator>
|
|
IR = ScratchRegsUsed.equal_range(MI);
|
|
for (ScratchRegsUsedTy::iterator I = IR.first; I != IR.second; ++I)
|
|
markRegisterUsed(I->second, RC, RegType, MRI);
|
|
|
|
// If there are implicit references, mark their allocated regs as well
|
|
for (unsigned z=0; z < MI->getNumImplicitRefs(); z++)
|
|
if (const LiveRange*
|
|
LRofImpRef = LRI->getLiveRangeForValue(MI->getImplicitRef(z)))
|
|
if (LRofImpRef->hasColor())
|
|
// this implicit reference is in a LR that received a color
|
|
RC->markColorsUsed(LRofImpRef->getColor(),
|
|
MRI.getRegTypeForLR(LRofImpRef), RegType);
|
|
}
|
|
|
|
|
|
/// If there are delay slots for an instruction, the instructions added after
|
|
/// it must really go after the delayed instruction(s). So, we Move the
|
|
/// InstrAfter of that instruction to the corresponding delayed instruction
|
|
/// using the following method.
|
|
///
|
|
void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
|
|
const MachineInstr *DelayedMI)
|
|
{
|
|
// "added after" instructions of the original instr
|
|
std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
|
|
|
|
if (DEBUG_RA && OrigAft.size() > 0) {
|
|
std::cerr << "\nRegAlloc: Moved InstrnsAfter for: " << *OrigMI;
|
|
std::cerr << " to last delay slot instrn: " << *DelayedMI;
|
|
}
|
|
|
|
// "added after" instructions of the delayed instr
|
|
std::vector<MachineInstr *> &DelayedAft=AddedInstrMap[DelayedMI].InstrnsAfter;
|
|
|
|
// go thru all the "added after instructions" of the original instruction
|
|
// and append them to the "added after instructions" of the delayed
|
|
// instructions
|
|
DelayedAft.insert(DelayedAft.end(), OrigAft.begin(), OrigAft.end());
|
|
|
|
// empty the "added after instructions" of the original instruction
|
|
OrigAft.clear();
|
|
}
|
|
|
|
|
|
void PhyRegAlloc::colorIncomingArgs()
|
|
{
|
|
MRI.colorMethodArgs(Fn, *LRI, AddedInstrAtEntry.InstrnsBefore,
|
|
AddedInstrAtEntry.InstrnsAfter);
|
|
}
|
|
|
|
|
|
/// Determine whether the suggested color of each live range is really usable,
|
|
/// and then call its setSuggestedColorUsable() method to record the answer. A
|
|
/// suggested color is NOT usable when the suggested color is volatile AND
|
|
/// when there are call interferences.
|
|
///
|
|
void PhyRegAlloc::markUnusableSugColors()
|
|
{
|
|
LiveRangeMapType::const_iterator HMI = (LRI->getLiveRangeMap())->begin();
|
|
LiveRangeMapType::const_iterator HMIEnd = (LRI->getLiveRangeMap())->end();
|
|
|
|
for (; HMI != HMIEnd ; ++HMI ) {
|
|
if (HMI->first) {
|
|
LiveRange *L = HMI->second; // get the LiveRange
|
|
if (L && L->hasSuggestedColor ())
|
|
L->setSuggestedColorUsable
|
|
(!(MRI.isRegVolatile (L->getRegClassID (), L->getSuggestedColor ())
|
|
&& L->isCallInterference ()));
|
|
}
|
|
} // for all LR's in hash map
|
|
}
|
|
|
|
|
|
/// For each live range that is spilled, allocates a new spill position on the
|
|
/// stack, and set the stack offsets of the live range that will be spilled to
|
|
/// that position. This must be called just after coloring the LRs.
|
|
///
|
|
void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
|
|
if (DEBUG_RA) std::cerr << "\nSetting LR stack offsets for spills...\n";
|
|
|
|
LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
|
|
LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
|
|
|
|
for ( ; HMI != HMIEnd ; ++HMI) {
|
|
if (HMI->first && HMI->second) {
|
|
LiveRange *L = HMI->second; // get the LiveRange
|
|
if (L->isMarkedForSpill()) { // NOTE: allocating size of long Type **
|
|
int stackOffset = MF->getInfo()->allocateSpilledValue(Type::LongTy);
|
|
L->setSpillOffFromFP(stackOffset);
|
|
if (DEBUG_RA)
|
|
std::cerr << " LR# " << L->getUserIGNode()->getIndex()
|
|
<< ": stack-offset = " << stackOffset << "\n";
|
|
}
|
|
}
|
|
} // for all LR's in hash map
|
|
}
|
|
|
|
|
|
void PhyRegAlloc::saveStateForValue (std::vector<AllocInfo> &state,
|
|
const Value *V, int Insn, int Opnd) {
|
|
LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap ()->find (V);
|
|
LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap ()->end ();
|
|
AllocInfo::AllocStateTy AllocState = AllocInfo::NotAllocated;
|
|
int Placement = -1;
|
|
if ((HMI != HMIEnd) && HMI->second) {
|
|
LiveRange *L = HMI->second;
|
|
assert ((L->hasColor () || L->isMarkedForSpill ())
|
|
&& "Live range exists but not colored or spilled");
|
|
if (L->hasColor ()) {
|
|
AllocState = AllocInfo::Allocated;
|
|
Placement = MRI.getUnifiedRegNum (L->getRegClassID (),
|
|
L->getColor ());
|
|
} else if (L->isMarkedForSpill ()) {
|
|
AllocState = AllocInfo::Spilled;
|
|
assert (L->hasSpillOffset ()
|
|
&& "Live range marked for spill but has no spill offset");
|
|
Placement = L->getSpillOffFromFP ();
|
|
}
|
|
}
|
|
state.push_back (AllocInfo (Insn, Opnd, AllocState, Placement));
|
|
}
|
|
|
|
|
|
/// Save the global register allocation decisions made by the register
|
|
/// allocator so that they can be accessed later (sort of like "poor man's
|
|
/// debug info").
|
|
///
|
|
void PhyRegAlloc::saveState () {
|
|
std::vector<AllocInfo> &state = FnAllocState[Fn];
|
|
unsigned ArgNum = 0;
|
|
// Arguments encoded as instruction # -1
|
|
for (Function::const_aiterator i=Fn->abegin (), e=Fn->aend (); i != e; ++i) {
|
|
const Argument *Arg = &*i;
|
|
saveStateForValue (state, Arg, -1, ArgNum);
|
|
++ArgNum;
|
|
}
|
|
unsigned Insn = 0;
|
|
// Instructions themselves encoded as operand # -1
|
|
for (const_inst_iterator II=inst_begin (Fn), IE=inst_end (Fn); II!=IE; ++II){
|
|
saveStateForValue (state, (*II), Insn, -1);
|
|
for (unsigned i = 0; i < (*II)->getNumOperands (); ++i) {
|
|
const Value *V = (*II)->getOperand (i);
|
|
// Don't worry about it unless it's something whose reg. we'll need.
|
|
if (!isa<Argument> (V) && !isa<Instruction> (V))
|
|
continue;
|
|
saveStateForValue (state, V, Insn, i);
|
|
}
|
|
++Insn;
|
|
}
|
|
}
|
|
|
|
|
|
/// Check the saved state filled in by saveState(), and abort if it looks
|
|
/// wrong. Only used when debugging. FIXME: Currently it just prints out
|
|
/// the state, which isn't quite as useful.
|
|
///
|
|
void PhyRegAlloc::verifySavedState () {
|
|
std::vector<AllocInfo> &state = FnAllocState[Fn];
|
|
int ArgNum = 0;
|
|
for (Function::const_aiterator i=Fn->abegin (), e=Fn->aend (); i != e; ++i) {
|
|
const Argument *Arg = &*i;
|
|
std::cerr << "Argument: " << *Arg << "\n"
|
|
<< "FnAllocState:\n";
|
|
for (unsigned i = 0; i < state.size (); ++i) {
|
|
AllocInfo &S = state[i];
|
|
if (S.Instruction == -1 && S.Operand == ArgNum)
|
|
std::cerr << " " << S << "\n";
|
|
}
|
|
std::cerr << "----------\n";
|
|
++ArgNum;
|
|
}
|
|
int Insn = 0;
|
|
for (const_inst_iterator II=inst_begin (Fn), IE=inst_end (Fn); II!=IE; ++II) {
|
|
const Instruction *I = *II;
|
|
MachineCodeForInstruction &Instrs = MachineCodeForInstruction::get (I);
|
|
std::cerr << "Instruction: " << *I
|
|
<< "MachineCodeForInstruction:\n";
|
|
for (unsigned i = 0, n = Instrs.size (); i != n; ++i)
|
|
std::cerr << " " << *Instrs[i];
|
|
std::cerr << "FnAllocState:\n";
|
|
for (unsigned i = 0; i < state.size (); ++i) {
|
|
AllocInfo &S = state[i];
|
|
if (Insn == S.Instruction)
|
|
std::cerr << " " << S << "\n";
|
|
}
|
|
std::cerr << "----------\n";
|
|
++Insn;
|
|
}
|
|
}
|
|
|
|
|
|
bool PhyRegAlloc::doFinalization (Module &M) {
|
|
if (SaveRegAllocState) finishSavingState (M);
|
|
return false;
|
|
}
|
|
|
|
|
|
/// Finish the job of saveState(), by collapsing FnAllocState into an LLVM
|
|
/// Constant and stuffing it inside the Module.
|
|
///
|
|
/// FIXME: There should be other, better ways of storing the saved
|
|
/// state; this one is cumbersome and does not work well with the JIT.
|
|
///
|
|
void PhyRegAlloc::finishSavingState (Module &M) {
|
|
if (DEBUG_RA)
|
|
std::cerr << "---- Saving reg. alloc state; SaveStateToModule = "
|
|
<< SaveStateToModule << " ----\n";
|
|
|
|
// If saving state into the module, just copy new elements to the
|
|
// correct global.
|
|
if (!SaveStateToModule) {
|
|
ExportedFnAllocState = FnAllocState;
|
|
// FIXME: should ONLY copy new elements in FnAllocState
|
|
return;
|
|
}
|
|
|
|
// Convert FnAllocState to a single Constant array and add it
|
|
// to the Module.
|
|
ArrayType *AT = ArrayType::get (AllocInfo::getConstantType (), 0);
|
|
std::vector<const Type *> TV;
|
|
TV.push_back (Type::UIntTy);
|
|
TV.push_back (AT);
|
|
PointerType *PT = PointerType::get (StructType::get (TV));
|
|
|
|
std::vector<Constant *> allstate;
|
|
for (Module::iterator I = M.begin (), E = M.end (); I != E; ++I) {
|
|
Function *F = I;
|
|
if (F->isExternal ()) continue;
|
|
if (FnAllocState.find (F) == FnAllocState.end ()) {
|
|
allstate.push_back (ConstantPointerNull::get (PT));
|
|
} else {
|
|
std::vector<AllocInfo> &state = FnAllocState[F];
|
|
|
|
// Convert state into an LLVM ConstantArray, and put it in a
|
|
// ConstantStruct (named S) along with its size.
|
|
std::vector<Constant *> stateConstants;
|
|
for (unsigned i = 0, s = state.size (); i != s; ++i)
|
|
stateConstants.push_back (state[i].toConstant ());
|
|
unsigned Size = stateConstants.size ();
|
|
ArrayType *AT = ArrayType::get (AllocInfo::getConstantType (), Size);
|
|
std::vector<const Type *> TV;
|
|
TV.push_back (Type::UIntTy);
|
|
TV.push_back (AT);
|
|
StructType *ST = StructType::get (TV);
|
|
std::vector<Constant *> CV;
|
|
CV.push_back (ConstantUInt::get (Type::UIntTy, Size));
|
|
CV.push_back (ConstantArray::get (AT, stateConstants));
|
|
Constant *S = ConstantStruct::get (ST, CV);
|
|
|
|
GlobalVariable *GV =
|
|
new GlobalVariable (ST, true,
|
|
GlobalValue::InternalLinkage, S,
|
|
F->getName () + ".regAllocState", &M);
|
|
|
|
// Have: { uint, [Size x { uint, int, uint, int }] } *
|
|
// Cast it to: { uint, [0 x { uint, int, uint, int }] } *
|
|
Constant *CE = ConstantExpr::getCast (ConstantPointerRef::get (GV), PT);
|
|
allstate.push_back (CE);
|
|
}
|
|
}
|
|
|
|
unsigned Size = allstate.size ();
|
|
// Final structure type is:
|
|
// { uint, [Size x { uint, [0 x { uint, int, uint, int }] } *] }
|
|
std::vector<const Type *> TV2;
|
|
TV2.push_back (Type::UIntTy);
|
|
ArrayType *AT2 = ArrayType::get (PT, Size);
|
|
TV2.push_back (AT2);
|
|
StructType *ST2 = StructType::get (TV2);
|
|
std::vector<Constant *> CV2;
|
|
CV2.push_back (ConstantUInt::get (Type::UIntTy, Size));
|
|
CV2.push_back (ConstantArray::get (AT2, allstate));
|
|
new GlobalVariable (ST2, true, GlobalValue::ExternalLinkage,
|
|
ConstantStruct::get (ST2, CV2), "_llvm_regAllocState",
|
|
&M);
|
|
}
|
|
|
|
|
|
/// Allocate registers for the machine code previously generated for F using
|
|
/// the graph-coloring algorithm.
|
|
///
|
|
bool PhyRegAlloc::runOnFunction (Function &F) {
|
|
if (DEBUG_RA)
|
|
std::cerr << "\n********* Function "<< F.getName () << " ***********\n";
|
|
|
|
Fn = &F;
|
|
MF = &MachineFunction::get (Fn);
|
|
LVI = &getAnalysis<FunctionLiveVarInfo> ();
|
|
LRI = new LiveRangeInfo (Fn, TM, RegClassList);
|
|
LoopDepthCalc = &getAnalysis<LoopInfo> ();
|
|
|
|
// Create each RegClass for the target machine and add it to the
|
|
// RegClassList. This must be done before calling constructLiveRanges().
|
|
for (unsigned rc = 0; rc != NumOfRegClasses; ++rc)
|
|
RegClassList.push_back (new RegClass (Fn, &TM.getRegInfo (),
|
|
MRI.getMachineRegClass (rc)));
|
|
|
|
LRI->constructLiveRanges(); // create LR info
|
|
if (DEBUG_RA >= RA_DEBUG_LiveRanges)
|
|
LRI->printLiveRanges();
|
|
|
|
createIGNodeListsAndIGs(); // create IGNode list and IGs
|
|
|
|
buildInterferenceGraphs(); // build IGs in all reg classes
|
|
|
|
if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
|
|
// print all LRs in all reg classes
|
|
for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[rc]->printIGNodeList();
|
|
|
|
// print IGs in all register classes
|
|
for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[rc]->printIG();
|
|
}
|
|
|
|
LRI->coalesceLRs(); // coalesce all live ranges
|
|
|
|
if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
|
|
// print all LRs in all reg classes
|
|
for (unsigned rc=0; rc < NumOfRegClasses; rc++)
|
|
RegClassList[rc]->printIGNodeList();
|
|
|
|
// print IGs in all register classes
|
|
for (unsigned rc=0; rc < NumOfRegClasses; rc++)
|
|
RegClassList[rc]->printIG();
|
|
}
|
|
|
|
// mark un-usable suggested color before graph coloring algorithm.
|
|
// When this is done, the graph coloring algo will not reserve
|
|
// suggested color unnecessarily - they can be used by another LR
|
|
markUnusableSugColors();
|
|
|
|
// color all register classes using the graph coloring algo
|
|
for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
|
|
RegClassList[rc]->colorAllRegs();
|
|
|
|
// After graph coloring, if some LRs did not receive a color (i.e, spilled)
|
|
// a position for such spilled LRs
|
|
allocateStackSpace4SpilledLRs();
|
|
|
|
// Reset the temp. area on the stack before use by the first instruction.
|
|
// This will also happen after updating each instruction.
|
|
MF->getInfo()->popAllTempValues();
|
|
|
|
// color incoming args - if the correct color was not received
|
|
// insert code to copy to the correct register
|
|
colorIncomingArgs();
|
|
|
|
// Save register allocation state for this function in a Constant.
|
|
if (SaveRegAllocState) {
|
|
saveState();
|
|
if (DEBUG_RA) // Check our work.
|
|
verifySavedState ();
|
|
if (!SaveStateToModule)
|
|
finishSavingState (const_cast<Module&> (*Fn->getParent ()));
|
|
}
|
|
|
|
// Now update the machine code with register names and add any additional
|
|
// code inserted by the register allocator to the instruction stream.
|
|
updateMachineCode();
|
|
|
|
if (DEBUG_RA) {
|
|
std::cerr << "\n**** Machine Code After Register Allocation:\n\n";
|
|
MF->dump();
|
|
}
|
|
|
|
// Tear down temporary data structures
|
|
for (unsigned rc = 0; rc < NumOfRegClasses; ++rc)
|
|
delete RegClassList[rc];
|
|
RegClassList.clear ();
|
|
AddedInstrMap.clear ();
|
|
OperandsColoredMap.clear ();
|
|
ScratchRegsUsed.clear ();
|
|
AddedInstrAtEntry.clear ();
|
|
delete LRI;
|
|
|
|
if (DEBUG_RA) std::cerr << "\nRegister allocation complete!\n";
|
|
return false; // Function was not modified
|
|
}
|
|
|
|
} // End llvm namespace
|